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Enquiries on writing veriloga

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suling

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Had started to learn to write veriloga. However, had some problems for the following. Would appreciate if someone can help.

1) Is there any limit on the number of buses to be define for a module? Had added in 4 buses with a<1:0>, b<2:0>, c<2:0> and d<5:0> and syntax error occurs, showing "Maximum allowable errors exceeded". However, the error disappear when remove c and d bus.

2) How to pass parameter to each bus? Are the following codes OK?

always @(a)
case (a)
2'b00: gain=25;
2'b01: gain=20;
2'b10: gain=15;
2'b11: gain=20;
endcase

Please advise.
 

Had written a small module as follows and errors prompt. Would appreciate if anyone can tell me what does the error means.

The objective is to pass the selection and ouput value accordingly. However, syntax errors shown:" Error found by spectre during SpectreHDL compile.

veriloga.va, line 28: "(V(en[1] == V(vdd12)) && (V(en[0]) == V(vdd12)))<<--?"
veriloga.va, line 28: Error: syntax error
veriloga.va, line 36: "V(out) <+ V(in)<<--? *c;"
veriloga.va, line 36: Error: vector operations are not yet supported
veriloga.va, line 36: Error: illegal access of simulator array quantity

Veriloa Code:
'include "constants.h"
'include "disciplines.h"

module a (vdd12, gnd, en, in , out);
inout vdd12, gnd;
input [1:0] en, in;
output out;

electrical vdd12, gnd;
electrical [1:0] en, in;
electrical out;

real c;

analog begin

if (V(en[1] == V(gnd)) && (V(en[0]) == V(gnd)))
c = 1;
elseif (V(en[1] == V(gnd)) && (V(en[0]) == V(vdd12)))
c = 2;
elseif (V(en[1] == V(vdd12)) && (V(en[0]) == V(gnd)))
c = 3;
else (V(en[1] == V(vdd12)) && (V(en[0]) == V(vdd12)))
c = 4;

V(out) <+ V(in) *c;

end
endmodule

Is there any website that I can refer to understand the error message?

Thank you in advance.
 

suling said:
veriloga.va, line 28: "(V(en[1] == V(vdd12)) && (V(en[0]) == V(vdd12)))<<--?"
Click to expand...
")" is lacking.

suling said:
veriloga.va, line 36: "V(out) <+ V(in)<<--? *c;"
Click to expand...
"in" is bus.
On the other hand, "out" is simple node.

Your module is very bad for your purpose.

Again see my append surely.
 

Hi, so sorry, typo error in the message, the bracket is there in the veriloga coding.

As seen in the declaration, "in" is an input, en is then the bus.
 

suling said:
As seen in the declaration, "in" is an input, en is then the bus.
Click to expand...
No. Both "in" and "en" are bus in your declaration.

The following is your declaration.
Code: 
input [1:0] en, in; 
electrical [1:0] en, in;
 

Hi, thank you for your advice. The function of this module is basically to take in 2 bits input from en, then determine the c value. The output will be V(in) when en<1:0>=00, 2*V(in) when en<1:0>=01, 3*V(in) when en<1:0>=10 and 4*V(in) when en<1:0>=11.

Had tried to clear the bus issue but syntax error still persists.
veriloga.va, line 32: "(V(en[1] == V(vdd12)) && (V(en[0]) == V(vdd12)))<<--?"
veriloga.va, line 32: Error: syntax error

Also, how to use the debugger as I was not able to see anything when I step thru.

Coding as follows:

// VerilogA for trial, a, veriloga

`include "constants.h"
`include "disciplines.h"

module a (vdd12, gnd, en, in, out);
inout vdd12, gnd;
//input [1:0] en, in;
input [1:0] en;
input in;
output out;

electrical vdd12, gnd;
//electrical [1:0] en, in;
electrical [1:0] en;
electrical in;
electrical out;

real c;

analog begin

if ((V(en[1]) == V(gnd)) && (V(en[0]) == V(gnd)))
c = 1;
else if
((V(en[1]) == V(gnd)) && (V(en[0]) == V(vdd12)))
c = 2;
else if
((V(en[1]) == V(vdd12)) && (V(en[0]) == V(gnd)))
c = 3;
else
(V(en[1]) == V(vdd12)) && (V(en[0]) == V(vdd12)))
c = 4;

//if (V(en) == V(vdd12))
// c = 1;
//else
// c = 0;

//$strobe("c is %g", c);

V(out) <+ V(in) * c;
end
endmodule
 


Hi, pancho_hideboo, had read thru your append. As I am new to this, sometimes I feel quite confusing on the syntax and limitation by veriloga as comapred to verilogams. Is there ways/helps that I can refer to check thru the code with description of errors clearly.

Added after 2 hours 6 minutes:

Hi, need help. Had changed the code to adapt for greater flexibility, but syntax error as shown
veriloga.va, line 10: "input [`Nbits<<--? -1] en
veriloga.va, line 10: Error: syntax error
Maximum allowable errors exceeded. Exiting AHDL compilation

// VerilogA for trial, a, veriloga

`include "constants.h"
`include "disciplines.h"

module a (vdd12, gnd, en, in, out);
`define Nbits 2;

inout vdd12, gnd;
input [`Nbits-1] en;
input in;
output out;

electrical vdd12, gnd;
electrical [`Nbits-1] en;
electrical in;
electrical out;

integer logic_value[0:`Nbits-1];
integer en_value;
real c;

genvar i;

analog begin

en_value = 0;
for (i=0; i<=`Nbits-1; i=i+1) begin
logic_value = (abs(V(en)-V(vdd12))<1e-3) ? 1 : 0;
en_value = en_value + logic_value*(1<<i);
end

case(en_value)
0: c = 1;
1: c = 2;
2: c = 3;
3: c = 4;
//4: c = 5;
//5: c = 6;
//6: c = 7;
//7: c = 8;
endcase


//$strobe("c is %g", c);

V(out) <+ V(in) * c;
end
endmodule

Added after 32 minutes:

Hi, error is fixed. Thanks for your help, pancho_hideboo.
 

suling said:
As I am new to this, sometimes I feel quite confusing on the syntax and limitation by veriloga as comapred to verilogams.
Click to expand...
I think you will make very easy mistakes even in Verilog-AMS or Verilog-D.

suling said:
Is there ways/helps that I can refer to check thru the code with description of errors clearly.
Click to expand...
Error messages from simulator are very clear to undesrtand errors in your code.

suling said:
module a (vdd12, gnd, en, in, out);
`define Nbits 2;
Click to expand...
You must not put ";" in the end of line.
Also you should not use "gnd" as node name.
Name of "gnd" is reserved in Verilog-AMS, although it is not reserved in Verilog-A.
I recommend you to use "ref" or "my_gnd" instead of "gnd".

Again see the following surely.
https://www.designers-guide.org/Forum/YaBB.pl?num=1266186403
 

Hi, can we have several assign variables within a case or if else statement? Is there any skip statement in veriloga?

The function of this module is to select the gain and NF depending on the bits of g_ctl if lna_en is "high", otherwise, the lna will be indicated as disabled.

syntax errors shown:

veriloga.va, line 47: "0: gain = 39; nf = 2.37; <<--? "
veriloga.va, line 47: Error: syntax error
veriloga.va, line 64: "endcase<<--? "
veriloga.va, line 64: Error: syntax error
file veriloga.va. Non-recoverable error: parser error: confused constext stack. Exiting AHDL compilation.

Added after 4 minutes:

Sorry, following are the codes.

// VerilogA for trial, a, veriloga

`include "constants.h"
`include "disciplines.h"

`define db20_real(x) (pow(10, (x)/20))
`define db10_real(x) (pow(10, (x)/10))

module a (vdd12, gnd1, lna_en, g_ctl, in, out);
`define Nbits 4

inout vdd12, gnd1, lna_en;
input [`Nbits-1:0] g_ctl;
input in;
output out;

electrical vdd12, gnd1, lna_en;
electrical [`Nbits-1:0] g_ctl;
electrical in;
electrical out;

integer logic_value[0:`Nbits-1];
integer gctl_value;

parameter real rin = 50 from (0:inf);

real a1,a2;
real s11, s12, s21, s22;
real nf;
real gain;

real rnf; // real NF
real noise_current;

genvar i;

analog begin

if (abs(V(lna_en) - V(vdd12)) < 1e-3)
gctl_value = 0;
for (i=0; i<=`Nbits-1; i=i+1) begin
logic_value = (abs(V(g_ctl)-V(vdd12))<1e-3) ? 1 : 0;
gctl_value = gctl_value + logic_value*(1<<i);
end

case(gctl_value)
0: gain = 39; nf = 2.37;
1: gain = 36; nf = 2.98;
2: gain = 33; nf = 3.00;
3: gain = 30; nf = 13.04;
4: gain = 27; nf = 16.31;
5: gain = 24; nf = 19.75;
6: gain = 21; nf = 23.55;
7: gain = 18; nf = 26.01;
8: gain = 15; nf = 28.24;
9: gain = 12; nf = 31.12;
10: gain = 9; nf = 12.60;
11: gain = 6; nf = 15.87;
12: gain = 3; nf = 19.37;
13: gain = 0; nf = 23.08;
14: gain = -3; nf = 25.45;
15: gain = -6; nf = 27.61;

endcase

else
$strobe("LNA is disabled")

s21 = -`db20_real(gain);
rnf = `db10_real(nf);
noise_current = 2*sqrt((rnf-1)*1.380620e-23*$temperature/rin);

//$strobe("gain is %g", gain);
V(out) <+ V(in) * gain;
end
endmodule
 

Make minimum efforts before posting questions.

suling said:
Hi, can we have several assign variables within a case or if else statement?
Is there any skip statement in veriloga?
Click to expand...
I can't understand what you want to mean.

suling said:
veriloga.va, line 47: "0: gain = 39; nf = 2.37; <<--? "
veriloga.va, line 47: Error: syntax error
Click to expand...
It has to be:
0: begin
gain = 39;
nf = 2.37;
end

This is same as Verilog-D and C-language, although "{ ~ }" is used instead of "begin ~ end" in C-language.

Again surely see https://www.designers-guide.org/Forum/YaBB.pl?num=1266186403


Enclose the followings by "@initial_step".
suling said:
s21 = -`db20_real(gain);
rnf = `db10_real(nf);
noise_current = 2*sqrt((rnf-1)*1.380620e-23*$temperature/rin);
Click to expand...
 

Hi, pancho_hideboo, really confusing, do not know if which document to follow. Had tried to follow close to the examples in the attached lecture notes below, don't see begin in case.
 

Your issues have no relation to "RF, Microwave, Antennas and Optics".
It is no more than very easy language syntax issue.

I recommend you to post your questions in http://www.designers-guide.org/Forum/YaBB.pl?board=verilogams

suling said:
really confusing, do not know if which document to follow.
Click to expand...
No one except for you have such confusion.

suling said:
Had tried to follow close to the examples in the attached lecture notes below, don't see begin in case.
Click to expand...
Document which you attached is "Training Manual".

See "Cadence Verilog-A Language Reference" not "Training Manual", since it seems you have Cadence Spectre.
Or see http://edocs.soco.agilent.com/display/ads2009/Analog+Block+Statements

You have to use "Sequential Block Statement".
This is true for "if", "for", "while", "case ~endcase", etc.

Requirement of "Sequential Block Statement" is very very very common sense in any language such as C-languge, Pascal, Verilog-D, etc.
This is a reason why there is no clear mention about "Sequential Block Statement" in "Training Manual".

Again surely see "example" of attached figure in http://www.designers-guide.org/Forum/YaBB.pl?num=1266186403/3#3
 

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