Effective W/L in Cadence Virtuoso

[mtwieg]

Hello, I've been using cadence for about five months now, and I'm now trying out designs with interdigitated/common centroid transistor layout. Recently while simulating a schematic view, I noticed that if I changed transistors to be fingered, but with the same drawn overall W/L, I would get much different behavior in DC biasing and transconductance. For example, if I have a current biased MOS diode with W/L=3/0.6 and M=1 and change it to W/L=1.5/0.6, M=2, I will find that its Vgs will increase significantly. Note that this is without actually doing any layout, extraction, or backannotation, these are purely specified parameters in the schematic view.

So the only explanation I can come up with is that cadence is somehow taking ΔW and ΔL into account in order to derive the effective W/L, which will depend on fingering. Does that sound right? If so, how can I see the effective W/L that cadence is deriving so that I can make adjustments? And how exactly does cadence know the ΔW and ΔL parameters? I'm using the NCSU C5X (on semi 0.5um) toolkit.

Thanks in advance.

 

[erikl]

... how can I see the effective W/L that cadence is deriving so that I can make adjustments? And how exactly does cadence know the ΔW and ΔL parameters?

From the dW and dL parameters in the transistor's model files. Depending on the used models and their complexity, dW and dL may depend on a lot of further parameters, s. e.g. this list from the BSIM3v3.2 Manual. See the manual on how dW and dL are calculated.

 

[mtwieg]

Hi erikl, that's pretty much exactly what I was looking for. I checked the spice model file for recent runs on my process and found that the only non-zero parameters were Wint and Lint, so it's a constant offset for both.

However, I'm not really sure that my NCSU toolkit uses the same model. I'll have to double check the tech library to make sure.

 

[erikl]

... found that the only non-zero parameters were Wint and Lint, so it's a constant offset for both.

Hi mtwieg, did you find out how complicated the dL, dW calculation from Lint & Wint values might be? See here a short explanation from the BSIM3v3.3 Manual:

 

[mtwieg]

Right I saw those formulas, but the models from MOSIS have all the Ww, Wl, Wwl parameters as zero, but Wint and Lint are not. I'm still looking in my cadence tech file to see what the parameters used by cadence are.

For example here's the most recent model parameters I can find from MOSIS for my process: https://www.mosis.com/cgi-bin/cgiwrap/umosis/swp/params/ami-c5/v29j-params.txt
Wint is >0.2um, which is very significant for a W=1.5um FET.

 

[erikl]

Wint is >0.2um, which is very significant for a W=1.5um FET.

Right, this is too wide for dW, I think you shouldn't take this for dW.

I found wint=lint=4e-08 in our 180nm process files, which sounds more reasonable for me.

 

[mtwieg]

Right, this is too wide for dW, I think you shouldn't take this for dW.

Well I did some simple IV curve simulation in cadence, and the results seem consistent with that dW...

I found wint=lint=4e-08 in our 180nm process files, which sounds more reasonable for me.

I'm dealing with 0.5um, so keep that in mind. In any case, this just means I have to widen some of my smaller transistors a little but, nothing critical.