[SOLVED] Verilog-A help in Cadence Virtuoso (SAR ADC)

[willshan02]

I am trying to write Verilog-A for a 5-bit SAR ADC which will act as a circuit block that controls the logic for the SAR algorithm and will output signals that control the switching on each capacitor. Here is what I have so far, I am getting syntax errors near the end with converting sar_out_int to a real variable so that I can map it to sar_out. Any ideas?

`default_transition 1n

module SARLOGIC (
  clk,
  start,
  comp,
  sar_out,
  switch_ctrl0,
  switch_ctrl1,
  switch_ctrl2,
  switch_ctrl3,
  switch_ctrl4,
  done
);

  input clk;
  input start;
  input comp;
  output sar_out;
  output switch_ctrl0;
  output switch_ctrl1;
  output switch_ctrl2;
  output switch_ctrl3;
  output switch_ctrl4;
  output done;

  integer sar_out_int;
  real sar_out_real;
  integer trial_code;
  integer bit_pos;
  integer done_int;

  analog begin
    @(initial_step) begin
      sar_out_int = 0;
      trial_code = 32;
      bit_pos = 5;
      done_int = 0;
    end

    @(cross($abstime - 0.5, 1)) begin
      if (start) begin
        sar_out_int = 0;
        trial_code = 32;
        bit_pos = 5;
        done_int = 0;
      end else if (done_int == 0) begin
        if (comp)
          sar_out_int = sar_out_int | trial_code;
        trial_code = trial_code >> 1;
        bit_pos = bit_pos - 1;
        if (bit_pos == 0)
          done_int = 1;
      end
    end

    // Assign outputs using contribution operator
    sar_out_real = $itor(sar_out_int);
    sar_out <+ $itor(sar_out_int);
    switch_ctrl0 <+ (trial_code & 1);
    switch_ctrl1 <+ ((trial_code >> 1) & 1);
    switch_ctrl2 <+ ((trial_code >> 2) & 1);
    switch_ctrl3 <+ ((trial_code >> 3) & 1);
    switch_ctrl4 <+ ((trial_code >> 4) & 1);
    done <+ done_int;
  end

endmodule

 

[sidun.av]

$itor directive does not exist in Verilog-A, it's a System Verilog function.
You can try to make your sar_out_real a voltage output and then add a sar_out_int value to it.