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Eeprom access problem

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rajesh6821

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I am working on AT89C51 & AT28C16 (eeprom). While interfacing AT89C51 to external EEPROM, I found 2 observations.

1. sometimes /CS is permenantly active i.e. address transition is not taking place but /WR & /RD signals are generated and the data is written properly to the EEPROM as per datasheet.
2. sometimes address transition is taking place but WR & /RD signals are not generated.

I am attaching thae circuit and code for your reference.

Please help me in this regard.
 

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  • EEPROM_ACCESS.pdf
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The purpose of the address decoder and /CS signal can't be understood from your schematic. The address lines A8-A15 are however only valid during memory accesses, so it's not surprizing to see /CS active sometimes. You can ignore this activities, or omit the decoder and tie /CS to low.
 

FvM said:
The purpose of the address decoder and /CS signal can't be understood from your schematic. The address lines A8-A15 are however only valid during memory accesses, so it's not surprizing to see /CS active sometimes. You can ignore this activities, or omit the decoder and tie /CS to low.
Click to expand...

The IC 7400 is a NAND gate and the signal Y is the output of NAND gate. When both a15 & a14 are high, then /CS is active. I don't understand what is the problem with this circuit Pls reply me.
 

I don't see power pins of 74LS273 in the schematic. Are they connected on your board?

How much delay is the delay() routine generating? Is it sufficient to allow internal EEPROM write operation to complete?
 
Last edited:

CMOS said:
I don't see power pins of 74LS273 in the schematic. Are they connected on your board?

How much delay is the delay() routine generating? Is it sufficient to allow internal EEPROM write operation to complete?
Click to expand...

Power pins of 74LS273 are connected on my board. The delay() routine gives 100 us delay but i tried with 1 ms delay routine also but I am facing same problem. Tell me what could be the problem?
 

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