Hi all,
In my design I'm looking for glitches on a test signal (ie signal goes |==|_|===| when it should go |======| if that made any sense :-D). Anyway I was using the following code
well anyway this works fine when the clk_in is faster than the glitch in the signal however its not able to detect an edge when the glitch is smaller than the clock period. Is there a better way to be doing this? Thank you
As long as the "glitches" high phase is longer than a system_clock_cycle you can be sure to detect each single pulse.
If you want to detect shorter pulses, then you need to treat the signal as a clock_input.
Maybe use a DFF with async_clear. DFF_clk is glitch_signal, DFF_D is 1.
Klaus
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Added:
I just see that FvM's solution is similar, but it needs no external clear.