flyingmonkey1
Newbie level 2
Hi all,
In my design I'm looking for glitches on a test signal (ie signal goes |==|_|===| when it should go |======| if that made any sense :-D). Anyway I was using the following code
well anyway this works fine when the clk_in is faster than the glitch in the signal however its not able to detect an edge when the glitch is smaller than the clock period. Is there a better way to be doing this? Thank you
In my design I'm looking for glitches on a test signal (ie signal goes |==|_|===| when it should go |======| if that made any sense :-D). Anyway I was using the following code
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module positive_edge_detector( input clk_in, input signal_in, output out_edge ); reg signal; always @ (posedge clk_in) begin signal <= signal_in; end assign out_edge = signal_in & (~signal); endmodule
well anyway this works fine when the clk_in is faster than the glitch in the signal however its not able to detect an edge when the glitch is smaller than the clock period. Is there a better way to be doing this? Thank you
Last edited by a moderator: