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Early Late Gate Clock synchronization

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KericWard

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Hello,
I have designed an Early Late Gate Clock synchronization with Matlab/Simulink. It is working so far, but only Phase Differences are corrected. There is a problem with compensating a frequency offset.
I think it is necessary to improve the design (gain of the VCO, filter parameters).
There is a lot of literature about the basics of Early Late Gate Clock synchronization.
But I found no in-depth information about Design Issues.
Can someone point me towards such kind of information?
 

Hi KericWard,

That depends of the amount of the frequency offset and the type of the loop.
General theory of PLL's apply. If the loop is of type 1, the locking range is limited when there is frequency offset.
You shoul try with small frequency offset and then increase it.
Floyd Gardner's book Phaselock Techniques explains the theory in an understandable way and has a chapter that nicely explains data synchronizers including Early-Late. (Other books about PPL's too.)
Regards

Z
 
Attached is a clock recovery circuit that track frequency and phase. It will swallow or add pulses to counter to achieve lock.

It's bandwidth is based on divider length (N). Worse case lock time is 1/2 N length.
 

Attachments

  • Data Clock Recovery Circuit 3.pdf
    1.5 MB · Views: 152
Hi KericWard,

Floyd Gardner's book Phaselock Techniques explains the theory in an understandable way and has a chapter that nicely explains data synchronizers including Early-Late. (Other books about PPL's too.)
Regards

Z

Many thanks for your reply. I have checked out the book Phaselock Techniques 3rd Edition by Floyd Gardner. But there are only two page about Synchronization of Data Signals in Chapter 17 Miscellaneous Applications of Phaselock Loop.
You mentioned a entire chapter about data synchronizers?
On which edition do you refer?
 

Hi KericWard

I had the 2nd edition in mind.
I just checked the 2nd and 3rd edition and they are quite different in several aspects. Gardner says in the preface of 3rd ed.:

Several parts of the second edition have been omitted: the chapters on optimization and synchronization, and the mathematical appendix.
...
Synchronization (recovery of carrier and clock from data signals), a major discipline of its own, was deemed to have grown too large to cover adequately in a book on phaselock loops. See Section 17.1 for a brief guide to synchronization.


I suggest you the 2nd edition, chapter 11 (Data Synchronizers), and the previous chapters presenting the basics of PLL.
Maybe the references given in sect. 17.1 of 3rd Ed. can be of interest.
Regards

Z
 
@zorro
Thanks again, for your reply. Quite a pitty that Gardner deleted the chapter about data synchronization in the latest edition. I will try to get a copy of the second edition in the university library.
 

Dear Mr
May you please send me via email the matlab/Simulink code that you have designed ,I really need it ,I will work on it to try to improve it,actually I am doing a research in time synchronization methods and what you will send to me will be extremely helpful for me. my email address is: hbenaouicha@yahoo.fr
Many Thanks and best regards
 

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