Dynamics and elaboration in Verilog

[sun_ray]

In case of generate statement in Verilog it is stated that "Generate statements allow Verilog code to be generated dynamically at elaboration time before the simulation begins". What is the dynamic here when it is stated here 'Generate statements allow Verilog code to be generated dynamically at elaboration time'? What is the dynamics here? What is this elaboration it is pointing to when it states 'Generate statements allow Verilog code to be generated dynamically at elaboration time'? What does this elaboration do before simulation. Is it any simulator do this elaboration by default before it does the verification?

 

[bharundi]

A compilation process generally has three phases - analyze, elaborate, and link - to build an executable (before simulation can be performed). In the elaboration phase, the compiler (i.e. VCS, NC-Verilog, ModelSim, etc.) expands the elements (Verilog code) under generate statements with the respect to the corresponding conditions, iterations, etc. of the generate statements. Generally, these conditional, iterative, etc. generate statements are controlled via module-level parameters; hence giving opportunities to the parent module(s) to configure the instance(s) of the parameterized module with generate statements dynamically by specifying different parameters (i.e. creating an instance of xyz_addr vs. abc_addr (conditional); or creating 5 instance of xyz_timers vs. 7 instances of xyz_timers (iterative)).

The dynamic nature here means that one instance of a module can be different from another instance of the same module based on the parameters provided for generate statements - making the module dynamic and not static (i.e. only one form). This is only applicable in the elaboration phase. This is somewhat similar to text macros (except for iterations, instance variability, etc.) that get processed in the analyze phase.

 

[sun_ray]

Bharundi


Thanks for the reply. I have some more question:

1. is it that all tools for synthesis, simulation, rtl check tools (like spyglass), PnR tools, STA tools (primetime) go through analyze, elabpration and link stage?

2. What do these tools do in elaboration phase? What do these tools do in analyze stage? What do these tools do in link stage?

3. How do you make this comment : "The dynamic nature here means that one instance of a module can be different from another instance of the same module based on the parameters provided for generate statements - making the module dynamic and not static (i.e. only one form). This is only applicable in the elaboration phase. This is somewhat similar to text macros (except for iterations, instance variability, etc.) that get processed in the analyze phase. " ? Is it from your past experience? Or, is it from some document where you have seen? Can you please send me those documents where is is explained in this way? Or, are you just trying to interprete in this way from you knowledge?

 

[bharundi]

This is where things start to get gray. Here are my best attempts to answer your questions.

1) I am not very familiar with all of the tools you mentioned here, but generally any tool wanting to make sense out of the design (and/or environment) has to go through some, if not all, stages of the process ('build' so called in the SW world). Please refer to the answer for 3) for more discussion.

2) In very general terms, a tool does the following in each phase. Again, it depends on the tool and how deep it needs to go in each phase based on the capabilities it needs to serve. Some are language-specific, and some are tool-specific.
Analyze Phase: A tool would analyze source code mainly for syntax errors, expansion of text macros, and such. Some tools create working/intermediate files for later use.
Elaboration Phase: A tool would stitch things (design components, verification components, and/or both) together. In this phase, the tool reports unresolved elements, if any. The intermediate files created in the analyze phase are further processes and a new set of intermediate files are creates (sometimes called object files).
Link Phase: A tool would link the intermediate (object) files created in the elaboration phase in addition with external libraries (needed by the tool and/or design/environment (PLI, CPI, DPI, etc. based library or extension of the environment or model).

3) The phases I mentioned are logical; some tools combine all in one process step or some split in two or even three. It all depends on the tool. Please refer to its documentation. Again, there could be a slight confusion regarding what is called compilation. I have used the term "compilation process" with the respect to "building" an executable for simulation, analysis (i.e. STA, Lint) or other purposes. I guess a more appropriate term would be "build", but then again it has its issues when it is generalized for all tools. Anyways, If you were to refer to the SystemVerilog spec (Section 3.12), then you would find what I called the Analyze Phase is actually referred as "Compilation". However, if you were to refer to a tool-specific documentation such as VCS, then it may be referred as "Analysis". So the answer to your questions is twofold: experience (and knowledge from the SW build process) and organizing things from you read in a tool documentation (or specification) to these phases (sometimes explicitly or implicitly mentioned).

Hope this will help to clear some of your questions.