Dynamically change PLL clock frequency on Cyclone IV

[Shuze Zhao]

Hi all, I'm wondering if there is a way I can change the system clock frequency dynamically? I assume we have to use the on-chip PLL to do so, if I'm not using external clock source? Not sure if Cyclone IV support dynamic frequency adjustment.

Thanks!

 

[vGoodtimes]

You should be able to do this in multiple different ways depending on your application. Reconfiguring the PLL will give you the most control, but seems to require the PLL be reset. I'm not sure if you need to gate off the clock output during this time in order to avoid glitches.

**broken link removed**

5-34 has some info on reprogramming the PLL from user logic.

 

[Shuze Zhao]

You should be able to do this in multiple different ways depending on your application. Reconfiguring the PLL will give you the most control, but seems to require the PLL be reset. I'm not sure if you need to gate off the clock output during this time in order to avoid glitches.

**broken link removed**

5-34 has some info on reprogramming the PLL from user logic.

Thank you so much! That's very helpful. Do you have any idea of what would be the settling time for PLL if I reconfig it dynamically?

 

[ads-ee]

Thank you so much! That's very helpful. Do you have any idea of what would be the settling time for PLL if I reconfig it dynamically?

It's stated somewhere in the documentation (which you should read). I recall it's something on the order of 100's of us to ms, before it stabilizes.

Or to put it bluntly if you need your clock to change frequency without glitches or stability problems then don't use the FPGA to do it. Use a VCXO.