msdarvishi
Full Member level 4
Hello everybody,
I would like to dynamically change the frequency of a logic module implemented into a Virtex FPGA. I found that that is possible through "MMCM Dynamic Reconfiguration Port (DRP)" or "PLL Dynamic Reconfiguration Port (DRP)" available as a primitive in Virtex fabric reported in Xilinx Application Notes. I would like to know is it possible to decrease the clock frequency dynamically by increasing the clock period with an arbitrary value? For example adding a specific delay into the CLK period to force the CLK to be dynamically reconfigured? If so, can you let me know how to do it?
Thanks,
I would like to dynamically change the frequency of a logic module implemented into a Virtex FPGA. I found that that is possible through "MMCM Dynamic Reconfiguration Port (DRP)" or "PLL Dynamic Reconfiguration Port (DRP)" available as a primitive in Virtex fabric reported in Xilinx Application Notes. I would like to know is it possible to decrease the clock frequency dynamically by increasing the clock period with an arbitrary value? For example adding a specific delay into the CLK period to force the CLK to be dynamically reconfigured? If so, can you let me know how to do it?
Thanks,