Dynamic Reconfigurable CLock Frequency in Virtex FPGAs

[msdarvishi]

Hello everybody,

I would like to dynamically change the frequency of a logic module implemented into a Virtex FPGA. I found that that is possible through "MMCM Dynamic Reconfiguration Port (DRP)" or "PLL Dynamic Reconfiguration Port (DRP)" available as a primitive in Virtex fabric reported in Xilinx Application Notes. I would like to know is it possible to decrease the clock frequency dynamically by increasing the clock period with an arbitrary value? For example adding a specific delay into the CLK period to force the CLK to be dynamically reconfigured? If so, can you let me know how to do it?

Thanks,

 

[FvM]

I wonder what you exactly mean by add "a specific delay into the CLK period"?

MMCM dynamic reconfiguration is available for PLL ("mixed mode clock manager") generated clocks. So firstly generate your clock through PLL, secondly find out the available options for changing it dynamically (e.g. frequency steps etc.).

That's where user manuals are made for.

- - - Updated - - -

I notice that Virtex-6 dynamic MMCM reconfiguration is restricted to integer PLL configurations and doesn't support fractional. So the range of available frequencies will be limited.

 

[msdarvishi]

I wonder what you exactly mean by add "a specific delay into the CLK period"?

MMCM dynamic reconfiguration is available for PLL ("mixed mode clock manager") generated clocks. So firstly generate your clock through PLL, secondly find out the available options for changing it dynamically (e.g. frequency steps etc.).

That's where user manuals are made for.

- - - Updated - - -

I notice that Virtex-6 dynamic MMCM reconfiguration is restricted to integer PLL configurations and doesn't support fractional. So the range of available frequencies will be limited.

Hello FVM,
Thanks for your reply. I mean istead of frequency divition with an integer number, is it possible to increase the clock period (Tclk) by a certain value and as a result decrease the frequency? For example for a design operation at 200MHz, the clock period is 5 nsec. Is it possible to add 0.1 nsec to the clock period and dynamically change the frequency??

Thanks.

 

[FvM]

You can't add exactly 0.1 ns to the period, but you possibly set the clock output to 196 MHz, depending on the PLL input frequency and the MMCM counter ranges which I'm not exactly aware of.

It's really necessary that you read the Virtex-6 clock manager user manual in thoroughly to understand the device features,