Dynamic logic AND gate

[circuitking]

Hi In TSMC 65nm, I have designed a dynamic Logic NAND gate and it is followed by an inverter(I used PMOS and NMOS same size) to make an AND gate. In a 3x8 decoder, when two of the inputs are logic 1, i.e, Ain2 = 1, Ain1 = 1 and Ain0=0. Ain2 and Ain1 are closer to Vdd and Ain0 is closer to ground. What I see in this case is that the output of NAND gate is pulled down and the inverter is inverting it. Clearly it is not doing its job correctly. I realized that I need to increase the transistor sizes in the inverter. Could someone confirm whether it is valid fix or am I missing anything? How do I decide how much should be transistor sizes in the inverter.

 

[BradtheRad]

Say you want output (high or low) to get within 5% of either supply rail.
Assign a reasonable load for your device. Say 1000 ohms. This means that an output transistor must become 50 ohms when turned on.

You must also make sure the other output transistor shuts completely off.

An experimental setup is a class A amplifier with a 1000 ohm resistor installed in the collector leg.