Duty Cycle Verilog Code Needs Help

[ntropy]

I have the following code that I'm trying to display the duty cycle of a signal (C15) at 1 MHz frequency.
Please help!!!!

Currently a_count counts and places its value in b_count to be readed. The ab_switch delay will be implemented at a later time.


/*****Duty Cycle Counter section *****/
// signals for counting the test clock C15
reg [31:0] a_count, b_count;
reg [25:0] one_second_count;
reg one_second_pulse, hundred_hertz_count, hundred_hertz_pulse, a_count_rst_count;
reg [3:0] ab_switch_delay;
reg a_count_ce, b_count_ce;
reg a_count_rst;
reg ab_switch;



always@(posedge C15)
begin
ab_switch_delay <= {ab_switch_delay[2:0], ab_switch};
case(ab_switch_delay[3:1])
3'b000: begin
a_count_ce <= 1;
b_count_ce <= 0;
end
3'b111: begin
a_count_ce <= 0;
b_count_ce <= 1;
end
default: begin
a_count_ce <= 1;
b_count_ce <= 0;
end
endcase
end

always@(posedge C15)
begin
// divide by 50,000,000 to generate pulse for reset
if(a_count_rst_count == 499)
begin
a_count_rst_count <= 'b0;
a_count_rst <= 'b0;
end
else
begin
a_count_rst_count <= a_count_rst_count + 1;
a_count_rst <= 1'b1;
end
end


always@(posedge C15 or posedge hundred_hertz_pulse)begin
if(a_count_rst == 1)begin
b_count <= a_count;
a_count <= 'b0;
end
else if(a_count_ce)
a_count <= a_count+1;
else
a_count <= a_count;
end


always@(posedge clk50)
begin
// divide by 50,000,000 to generate pulse
if(one_second_count == 26'd49999999)
begin
one_second_count <= 'b0;
one_second_pulse <= 1'b1;
end
else
begin
one_second_count <= one_second_count + 1;
one_second_pulse <= 1'b0;
end
end

always@(posedge clk50)
begin
// divide by 50,000,000 to generate pulse
if(hundred_hertz_count == 499)
begin
hundred_hertz_count <= 'b0;
hundred_hertz_pulse <= 1'b1;
end
else
begin
hundred_hertz_count <= hundred_hertz_count + 1;
hundred_hertz_pulse <= 1'b0;
end
end
/***** User Controls section *****/
wire [7:0] user_ctrl_en; // 8 seperate enables controlled via GUI
wire [15:0] user_ctrl; // 16-bit value entered via GUI
reg [127:0] user_status=0; // 16 bytes of status that reported back to GUI
wire user_ctrl_stb; // strobe to signal when user controls written
always @(posedge clk125)
if (user_ctrl_en[0]) begin
user_status <={b_count[31:24],b_count[23:16], b_count[15:8], b_count[7:0],"%"}; end