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primetime dynamic timing analysis
DSP Based SoC Static/Dynamic Timing Analysis
Using PrimeTime/PowerMill
Yaacov Kobrinsky, Eli Ofek
DSP Group, Inc Israel
ABSTRACT
Our DSP based System On a Chip (SoC) is aimed at achieving the best cost-performance for a
given silicon area, taking into account memories area size (ROM/RAM), “glue logic” (ASIC
portion), smart power management, interfacing techniques timing budgeting, etc. The migration
to process 0.25 (or less) micron process has put severe timing and power constraints particularly
on the “core”, which is a relatively small part of SoC design. Appropriate design needs to
consider timing constraints at chip-level in order to take into account real output loads, input
transitions and other boundary conditions. This makes full chip timing analysis obligatory. The
peculiarity of DSP design is that it includes both digital and analog parts which makes it
impossible to limit timing analysis to static timing verification. In order to compress design
schedules from the end of layout to tapeout sign-off, highly automated design flows are needed to
build debugging environments for solving full-chip level timing/power problems. Our proposed
solution is to integrate timing verification tools (PrimeTime, PathMill) and dynamic simulation
tools (PowerMill) in one flow that attains several goals: checks the consistency of input data,
customizes the reports, builds timing views of subdesigns, generates boundary constraints for
both P&R and DC, translates functional tests into input patterns and accepts design queries for
examining the waveforms on internal nets. In this paper we present a design methodology that is
supported by this flow and the examples of timing / power analysis.
DSP Based SoC Static/Dynamic Timing Analysis
Using PrimeTime/PowerMill
Yaacov Kobrinsky, Eli Ofek
DSP Group, Inc Israel
ABSTRACT
Our DSP based System On a Chip (SoC) is aimed at achieving the best cost-performance for a
given silicon area, taking into account memories area size (ROM/RAM), “glue logic” (ASIC
portion), smart power management, interfacing techniques timing budgeting, etc. The migration
to process 0.25 (or less) micron process has put severe timing and power constraints particularly
on the “core”, which is a relatively small part of SoC design. Appropriate design needs to
consider timing constraints at chip-level in order to take into account real output loads, input
transitions and other boundary conditions. This makes full chip timing analysis obligatory. The
peculiarity of DSP design is that it includes both digital and analog parts which makes it
impossible to limit timing analysis to static timing verification. In order to compress design
schedules from the end of layout to tapeout sign-off, highly automated design flows are needed to
build debugging environments for solving full-chip level timing/power problems. Our proposed
solution is to integrate timing verification tools (PrimeTime, PathMill) and dynamic simulation
tools (PowerMill) in one flow that attains several goals: checks the consistency of input data,
customizes the reports, builds timing views of subdesigns, generates boundary constraints for
both P&R and DC, translates functional tests into input patterns and accepts design queries for
examining the waveforms on internal nets. In this paper we present a design methodology that is
supported by this flow and the examples of timing / power analysis.