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Driving very high loads with op-amp

Junus2012

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Dear friends,

Through my study for the filter design, I found nice document by texas instrument shown below


In figure 29 they give an example óf designing a low pass filter with fc = 1 MHz. The passive elements used to construct the active filters is very big like using capacitors in size of 220 PF and 100 PF.

I wonder how the op-amp is able to drive such big values with GBW that should be sufficient, The op-amp used for this design is THS4141 that has 160 MHz, but the company didn't specifiy the capacitive load for this test.

Thank you very much
 

FvM

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220 pF ist kOhm impedance at 1 MHz, not very big, just appropriate for low noise circuit.
 

    Junus2012

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Dominik Przyborowski

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ua790 is an ua741 with stronger output stage driving 1A. 220pF is a very small Capacitor in real (discrete) world.
 

    Junus2012

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Junus2012

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Dear friend,

I want to desing an opam for the same filter characteristics built by CMOS integrated circuits,

Just imagine If I want to design a two stage amplifier to drive such a capacitor and has to satisfy the GBW condition, beside it has compensation capacitor,,
as generally, GBW = gm1/2.pi.CC, where CC is the compensation capacitor

Here we will have a very big integrated CC, which is the first problem,

secondly gm needs to be very high and high current needed to satisfy the GBW and the SR later on.

When I read in literature, books or papers, I find people are afraid of several tens of PF in CMOS IC design, that is why I see these value like unfamiliar with me
 

KlausST

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Hi,

So I summarize your specifications:
* the same filter characteristics
* amplifier to drive such a capacitor
* has to satisfy the GBW condition
* it has compensation capacitor
* we will have a very big integrated CC
* GBW = gm1/2.pi
* gm needs to be very high
* high current needed to satisfy the GBW and the SR

Put all these values in a simulation tool and see what comes out...

Please tell me why you write just vague informations? What can we and what can you gain by them?

Klaus
 

Dominik Przyborowski

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Attached document shows design example using discrete components. It is very hard to get single pF in discrete Capacitor, so it's natural to use values in nF range.
In contrary, in IC world is hard to achieve more than single pF, so conclusion is simple. If you want to copy discrete design to IC, scale components - caps down, resistors up.
 

Junus2012

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Attached document shows design example using discrete components. It is very hard to get single pF in discrete Capacitor, so it's natural to use values in nF range.
In contrary, in IC world is hard to achieve more than single pF, so conclusion is simple. If you want to copy discrete design to IC, scale components - caps down, resistors up.
Thank you friends,

yes the attached document gives an example of a discrete design, and you are right, I should decrease capacitor and increase R for IC.

But even with capacitors in terms of several tens of picos, I am struggeling to reach high GBW needed by the active RC filter,

I have tried the WEBENCH filter designer from texas instrument to design 4th order MFB LPF with fc = 5 MHz. Although the tools is dedicated for the dicreate filter wizard design, but gives useful information that is the same applied for IC design as well, in the attached image you see the suggested GBW of the two Op-amp needed for the implementation, just tell me please how can I afford such values in CMOS 0.35 µm technology? specially for the second op-amp looks like I can not reach this GBW even in my next birth.

This led me to other question, why the tools assume two different GBW, why the second stage must have higher GBW if both process the same fc?

Thank you in advance

filter.PNG
 

sutapanaki

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It is probably because the second stage has higher Q factor for the poles. However, as I suggested to you long time ago, you should create parametrized opamp model, build you filter and explore the sensitivity of the filter characteristic to the parameters of the opamp.
 

Dominik Przyborowski

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You can move opamp nonidealities (finite gbw) to feedback elements. This few hundred MHz GBW ensures gain >40dB at fc making filter insensitive to opamp parameters (at least with tolerance better than 1%).

By using slower opamp, you will need to modify ratios in feedback to keep Q factor high enough. Again, as stated above - check filter sensitivity on various parameters.

Your process has ft on level of 10GHz for NFETs, so 500MHz UGF is achievable by single stage. With 1mA current consumption, simple Miller OTA can get at least 70MHz driving 10pF with 60deg phase margin.

If you want to optimize amplifier for speed, check for what biasing condition your mosfets reaching peak ft. Testbench can be found both on this forum and cadence blogs as well.
 

Junus2012

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Dear friends,

I thank you very much for your help,

You can move opamp nonidealities (finite gbw) to feedback elements. This few hundred MHz GBW ensures gain >40dB at fc making filter insensitive to opamp parameters (at least with tolerance better than 1%).


Your process has ft on level of 10GHz for NFETs, so 500MHz UGF is achievable by single stage. With 1mA current consumption, simple Miller OTA can get at least 70MHz driving 10pF with 60deg phase margin.

The problem I can't use single stage OTA because I need to drive resistive feedback load,

you have stated that two stage Op-Amp can get at least 70 MHz with 10 pF, which still far away from value like 270 MHz or 653 MHz, if you suggesting me to reduce the feedback capacitive vlaues it might be managable but in the same time I can not ignore the load from the next stage ADC that is in the order of 10 pF.

Please see the below image, of the filter given by the manual, considering these values in figure (A), I need your help to have an approxiamation values in Fig (B), this will help me to design an accurate op-amp.

filter_1.jpg


If you want to optimize amplifier for speed, check for what biasing condition your mosfets reaching peak ft. Testbench can be found both on this forum and cadence blogs as well.
it will be great if you please direct me to some links, I never used to design op-amp for only speed optimization, is that about gm/ID methos ?
 

sutapanaki

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gm/Id is a method of design not specifically targeted to speed only. It can be used fo any corner of the design space. Speed too.
 

Junus2012

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Please friends expand my post in #10 to see the complete comment
 

Dominik Przyborowski

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You are doing everything awry.
Have you spec numbers for your noise and input impedance? They gives you a constraints for min resistors in filter. Caps are chosen in respect of resistors. Simulate opamp in filter environment.
Some threads ago you get recommendation to make behavioral simulations to get all respected numbers for opamp spec and check sensitivity of filter design on RC and opamp tolerance.
Have you done it? Have you a numbers?

ft is symbol for transit frequency one of the most principal transistor's parameter. It is explained in every book. As long as ft>>design BW we can use Giacoletto small signal model and calculate transfer function of Amplifier.

In 0.35um CMOS 1GHz GBW is achievable, however even if you get opamp with only 50MHz then your filter will operate properly but will need to have aligned cap values (like smaller C2 than for ideal case)
 

Junus2012

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Dear Dominik

Thank you for your help

Indeed Suta suggested me to create a Verilog module to simulate the required op-amp but we are facing some bugs in the Cadence system that not allowing me to work with the Verilog. our technician is in vacation so I am using the time to search and design.


In your post #09 you clearly explained why needing higher GBW of several hundreds MHz above the fc, I also read the article from Texas instrument where I found the answer for my post, for Q > 1 the GBW should be safe enough to provide at least 40 dB loop gain at the peak value of Q, hence the required GBW = 100*fc*Gain*Q where 100 stands for the 40 dB.

in another article from Texas they stated (as you also suggested in your last post)that working with less GBW is possible, the fc mostly will not be effected too much but the Q would shift specially for high Q stage, means it will drop. They suggested a solution to use higher Q than required to compensate this drop to the desired value.

I would say this issue is becoming clear now, thank you guys for explaining it to me.

The one which still not clear and indeed very important (I also made seperate post for it), is the GBW of the selected op-amp from a company (just as an example), say I ordered one with GBW = 500 MHz, but how I will be sure that this value will stay the same after connecting my filter feedback elements, may be I am connecting capacitors in terms of several nano farads, others may be several hundreds pF or other several tens pF. The GBW is not going change ? if it is changing then might be I am ordering one with 500 MHz but after connecting the feedback it becomes 50 MHz (specially with high feedback capacitor)


Thank you very much
Please forgive me if you see me asking selly or very basic questions,

Best Regards
 

sutapanaki

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You don't need to create VerilogA model for the opamp. You can create a model using only components from analogLib, like vcvs (or vccs), resistors and capacitors.
As for your other question - the feedback network is there to realize your function, in this case a filter. I think you can safely split the problem in two parts. An opamp with given UGBW and the feedback. Most often the UGBW is defined by the compensation capacitor in the opamp, not by the load. The load affects the non-dominant pole. But in complicated circuits these effects can be best seen with simulations.
 

Junus2012

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As for your other question - the feedback network is there to realize your function, in this case a filter. I think you can safely split the problem in two parts. An opamp with given UGBW and the feedback. Most often the UGBW is defined by the compensation capacitor in the opamp, not by the load. The load affects the non-dominant pole. But in complicated circuits these effects can be best seen with simulations.
Thank you Suta for your reply,

That is also what I was expecting, it is true that GBW of the multistage amplifier is defined by the compensation capacitor (CC), not by the load. However, the CC is designed for certain CL, the higher CL the higher CC op-amp need for the compensation, so I am thinking that what is the criteria on defining the GBW while it is not shown at which CL is tested.

A company can make the CC very small and so the GBW is looking very high, while other company used higher CC so their GBW is looking less, same will be applied for the transient performance.

As for me to design the filter op-amp myself, I am targetting GBW of 250 MHz, let me use the simple approxiamation

GBW = gm / (2 pi CL)

with two stage op-amp CC about 0.25 CL.

See here how I need to understand the load CL, is my load include the filter feedback capacitors ? or CL means only the input capacitive of the next stage.

If I am not not wrong, I understood from your last post that feedback element " the feedback network is there to realize your function, in this case a filter " which means that feedback elements is separated from the calculation of GBW during the design

Thank you once again

Regards
 

sutapanaki

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I'll correct your formula to GBW = gm / (2 pi Cc) for a two stage opamp. It is true that CL affects the GBW somewhat but this happens through the position of the non-dominant pole of the loop, for example if you have the amplifier connected as a follower. Cc is usually sized not only based on GBW and non-dominant pole but also based on noise. All up to here is what concerns the amplifier itself. When you wrap your filter feedback around the amplifier the loop gain changes, of course and it should change because you want to build now a totally different transfer function and your amplifier with its transfer function, GBW and non-dominant pole is just part of it.
 

Junus2012

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Thank you Suta for your correction and your kind help,

yes it is GBW = gm / (2 pi Cc)

This statement is very useful to me " When you wrap your filter feedback around the amplifier the loop gain changes, of course and it should change because you want to build now a totally different transfer function and your amplifier with its transfer function, GBW and non-dominant pole is just part of it "

I can conclude that to design the two-stage amplfier of the filter, I will assume I have a load equal to the input of the next stage which is the ADC, so I will presume it 10 pF (and for sure able to drive resistive load). I will compensate the amplifier for this range and to reach for the required bandwidth.
By this way I will not think in advance about the filter capacitive values, as you said, it will by any way change the transfer function.

Thank you once again
 

sutapanaki

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Before you design your amplifier with transistors build a model of it, put in the model the GBW, the DC gain and the non-dominant pole which you think you can achieve and test it with your filter.
 
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