DRC rules for Double Pattern Test

aditya1579 · May 25, 2020

Hi All,

Can anyone list out a few DRC rules specially formulated for double patterning in lower tech nodes like 7nm etc ?

Thanks,
Aditya

ThisIsNotSam · May 25, 2020

aditya1579 said:
Hi All,

Can anyone list out a few DRC rules specially formulated for double patterning in lower tech nodes like 7nm etc ?

Thanks,
Aditya

The most important rule is MxC1 to MxC2 distance (versus MxC1 to MxC1)
Forbidden pitch rules are also very tricky
odd cycle violations

check this link: https://semiengineering.com/cut-cut-double-patterning-question/

CambridgeLv · May 29, 2020

As you know, foundry use 2 masks successively to make one layer on chip, so each metal will have 'perfect direction', same masks with large space compared with different masks with small space, of course some
forbidden space and width.
For more details, you can check foundry design rules.

DRC rules for Double Pattern Test

aditya1579

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ThisIsNotSam

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CambridgeLv

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DRC rules for Double Pattern Test

aditya1579

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ThisIsNotSam

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CambridgeLv

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