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DRC rules for Double Pattern Test

aditya1579

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Hi All,

Can anyone list out a few DRC rules specially formulated for double patterning in lower tech nodes like 7nm etc ?

Thanks,
Aditya
 

ThisIsNotSam

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CambridgeLv

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As you know, foundry use 2 masks successively to make one layer on chip, so each metal will have 'perfect direction', same masks with large space compared with different masks with small space, of course some
forbidden space and width.
For more details, you can check foundry design rules.
 

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