dpram without inferring a memory block from fpga

[aravi.ab]

hi all,
I am new to fpga and vhdl. I am trying to design dpram without inferring a block memory.But if I use 2d array in vhdl,While synthesizing the code it automatically inferred the block ram.I want to do it with only registers.



thanks

 

[Alexium]

Out of curiousity: what's dpram? Dual port?

---------- Post added at 23:32 ---------- Previous post was at 23:18 ----------

If you want to ensure RAM will be synthesised as distributed - make it asynchronous. That much I can guarantee. In fact, it's quite hard to make synthesis tool create a BRAM. I was experimenting earlier today, and I wasn't able to get Xilinx XST synthesise RAM module as BRAM no matter how hard I tried...

 

[FvM]

You should be able to use global settings and instance specific synthesis attributes to control RAM inference. At least it works well with Altera Quartus.

 

[Brownout]

Please show your code and tell us which FPGA vendor your're working with ( Xilinx, Altera )

 

[amitjagtap]

I assume you are using xilinx.
In ISE you can use planAhead tool to place your design. in this you can drag and drop set of nets to particular primitives.
So select your DPRAM and place it on distributed RAM. You want higher version of xilinx(may be 10 and above).
But note that distributed RAM is less in quantity as compared to block RAM. So you can not have large distributed DPRAM