Doubt regarding synthesis of RAM

[research_vlsi]

synthesis doubt

Dear friends

am having a doubt regarding synthesis of RAM.. i given the code below.

in the case am trying to reset the RAM to zero before i read/write.

module ram(reset,clk,read,var1,var2,address1,datain,wr_en,address2,dataout);

parameter width = 32, depth = 64 , state0=1'b0, state1=1'b1;
input reset,clk,read,wr_en;
input [15:0] var1, var2;
input [31:0] address1,address2;
input signed [31:0] datain;
output reg signed [31:0] dataout;
reg signed [width-1:0] mem [0:depth-1];
reg [15:0] temp;
reg state;

always @ (posedge clk)
begin
if(reset)
begin
state<=state0;
temp<=0;
dataout <=0;
end
else
begin
case(state)
state0:begin
if(temp<depth)
begin
mem[temp]<=0;
temp<=temp+1;
state<=state0;
end
else
state<=state1;
end
state1:begin
if(var1==0 && var2==1)
begin
state<=state0;
temp<=0;
end

else
state<=state1;
end
default: state<=state0;
endcase

if(read && ~wr_en)

dataout <= mem[address2];

else if(wr_en && ~read)

mem[address1] <= datain;

end
end
endmodule

tool am using is xilinx XST demo, the code is synthesizing but am not able to infer RAM in schematic, its coming fully registers/FF.

without that case logic for reseting am able to get RAM in schematic, but i want to reset the RAM to Zero before read/write. any alternate logic is there?. also i tried that case logic in separate always block, am getting fatal error. so any solution?

thanks

 

[asicganesh]

synthesis doubt

Hi
If you want to infer the underlying Block RAM's, you can refer the below document

https://www.xilinx.com/support/documentation/white_papers/wp231.pdf

To my knowledge XST never infers a BRAM in any mode if we have external reset..

try removing the reset input signal from your module.. it should infer a BRAM/Distributed RAM..

 

[research_vlsi]

Re: synthesis doubt

thanks ganesh..

 

[echo47]

synthesis doubt

Also see chapter "HDL Coding Techniques" in your XST User Guide. If shows various syntax examples that help XST infer Block RAM.

These three lines all access the RAM, although perhaps at different times:
mem[temp]<=0;
mem[address1] <= datain;
dataout <= mem[address2];
That may look too much like three-ported RAM for XST to figure out how to infer a two-port Block RAM.

 

[FvM]

Re: synthesis doubt

Hello,

I'm not particular familiar with XILINX tools, but I guess it won't be able to infer dual port RAM. This would be needed for the shown design, cause the initial reset process and normal operation (which has mutual exclusive read and write and could be realized as single port) are parallel.

With read/write enabled in state1 only, it would be effectively changed to a single port design, but I don't know if XST could recognize it without additional "hints". The other option would be to use a static power on initialisation of RAM instead of a reset initialisation process, if applicable.

Regards,
Frank