amriths04
Full Member level 5
i have to design a 10 bit resolution , a 1.5 bit per stage 100MEGA samples per second pipelined adc. i decided to use opamp sharing technique..
i had written my design equations, please tell whether i am right or wrong..
first i chose the sampling cap and feedback cap values in the following manner.
4kt/Cs << (del)^2 / 12... where del = step size = 2Vref/(2^10 - 1 )..
Vref=1V(pp,diff).
i got Cs >> 56fF. so i chose Cs = 400fF.
since i want my closed loop gain(Acl) as 2, i took feedback factor(beta) = 0.5.
so Cs = Ci for beta to be 0.5.
next how should i proceed? is all what i did till now right?
------- another doubt is that i had taken my step-size(in noise calculation) to be 2Vref/(2^10 - 1).. but in a single stage the step size should be 2*Vref/(2^2 - 1) only right?
please correct me if i am wrong..
thank you in advance,
i had written my design equations, please tell whether i am right or wrong..
first i chose the sampling cap and feedback cap values in the following manner.
4kt/Cs << (del)^2 / 12... where del = step size = 2Vref/(2^10 - 1 )..
Vref=1V(pp,diff).
i got Cs >> 56fF. so i chose Cs = 400fF.
since i want my closed loop gain(Acl) as 2, i took feedback factor(beta) = 0.5.
so Cs = Ci for beta to be 0.5.
next how should i proceed? is all what i did till now right?
------- another doubt is that i had taken my step-size(in noise calculation) to be 2Vref/(2^10 - 1).. but in a single stage the step size should be 2*Vref/(2^2 - 1) only right?
please correct me if i am wrong..
thank you in advance,