doubt regarding a data register

[praneeth87]

hi all,
I have a problem in implementing a data register with respect to the spec given to me. The data regsiter can hold data of 1 byte (8 bits) of data. I need to design the data register in such a way that the writing into it is done in 25 Mhz frequency and the reading out of it is done at 2 Mhz. Is it possible to design this type of register. Since the register is an ordinary 8 bit flip flop . Can it write at one speed and read at another speed because a flip flop can operate with only one clock(only one frequency) and I am not allowed to use a FIFO because the spec strictly mentions an ordinary data register should be designed. Please give some suggestions.

 

[majestic.eda]

You can put a mux in the clock path of a simple register like this:

CLK = (READ . CLK_RD) + (WRITE . CLK_WR)

where READ and WRITE are active-high read/write signals for reading data from this register, and CLK_RD & CLK_WR are the 2MHz & 25MHz clocks respectively. CLK will be the wire that is connected to the data register ultimately. It is assumed that READ/WRITE signals are always complementary of each-other.

But this solution has one disadvantage. It will cause a clock skew in your system.

 

[FvM]

What makes you think that reading of a FF involves a clock?

 

[lostinxlation]

Flop outputs are always on. it's just a matter of what clock captures the data present on flop output and you only need to careful to avoid metastability.

 

[majestic.eda]

Sorry... my reply was complete nonsense.. didnt give much thought.

The two replies above are correct.. U don't need a clock to read FF o/p. They are always ON.

 

[kalyanasv]

An easy way to ensure there are no clock issues you need to ensure both the clock are in phase. Considering 25Mhz is not a perfect multiple of the 2Mhz. You could have phase issue. You could use a PLL to lock the phase of the 2MHz using the 25MHz.

A cheeky way, which works for temp solution (FPGA's) is by using a double FF of the lower clock with the higher clock i.e. 2MHz -> edge FF_25MHz ->edge FF_25MHz -> latched 2MHz version. This is not the best way to do it in an ASIC.