doubt in set_clock_uncertainty constraint

[sumanth495]

hi friend,

while writing "set_clock_uncertainty" command, we will write seperate values for setup & hold.
i have observed that, in most of the cases setup uncertainity is more compared to hold.

is there any specific reason for it????

eg:
set_clock_uncertainty -setup 0.15 [get_clocks Hclk]
set_clock_uncertainty -hold 0.1 [get_clocks Hclk]

thanks in advance

--Sumanth

 

[dftrtl]

Unceratinity between two clock edges is more because of PLL jitter and CTS jitter. i.e is SETUP
Same clock has less uncertainity on same edge, this is how pll behaves i.e is HOLD

 

[sumanth495]

Unceratinity between two clock edges is more because of PLL jitter and CTS jitter. i.e is SETUP
Same clock has less uncertainity on same edge, this is how pll behaves i.e is HOLD

hi dftrtl,

thanks for your reply. can you please elaborate it so that i can understand better.

 

[dftrtl]

Two edges of PLL will differ sue to jitter which is setup uncertainity. Where as only one edge which is considered for both capture and launch in HOLD has no PLL jitter

 

[praveen.kumar432]

Hi Fnd,

uncertainty will have 2 diff quintettes
1) Before cts treated as : Jitter+ Skew
2)After cts treated as : Jitter

Def Jitter:variation of edge in the clock from source point,ex: period 2,clock edges 0,2,4,6,8,...etc(ideal). In the real world no ideal component so from PLL edge may comes before 0 or after 0.that variation called jitter.

setup: will consider a clock period at Capture edge, so jitter will be larger component.
Hold: same edge(Lanch and Capture) means what ever variation in the Lanch Edge same replica will be in Capture Edge.Jitter will less value.

Please correct me if wrong