i am using quartus . i had a design running at 65 Mhz clock . so when i write the sdc file what should be the time period ???
actual calculation its 15.384615...... ns . so what should i do to get exact 65 mhz clock so that timing violations wont come.
how to select the time period for 65 Mhz clock?
15.384 should be good enough.
Or just set it to 15 - this will slightly overconstrain the design, and if it can meet this timing, then it will work with a slower clock.