[SOLVED] doubling frequency in digital circuit

[prsk]

To double frequency, we can exor the output of one ff and output of another ff whose o/p is delayed by quarter time period of original clock. How to achieve this delay of quarter time period?

 

[FvM]

More easily, the frequency doubling can be achieved with a single XOR gate and a delay element. The latter is the problem, of course. You might use logic cell delay, involving the usual PVT (process, voltage, temperature) induced delay variations.

Ultimately, a PLL is the way to generate multiplied frequencies with precise duty cycle.

 

[prsk]

More easily, the frequency doubling can be achieved with a single XOR gate and a delay element. The latter is the problem, of course. You might use logic cell delay, involving the usual PVT (process, voltage, temperature) induced delay variations.

Ultimately, a PLL is the way to generate multiplied frequencies with precise duty cycle.

Ok! that is valid but how would you do it using flip flop or latch? purely digital ckt

 

[FvM]

What's the difference with using FFs? I don't see any. The delay has to be generated in an "analog"way either, e.g. by logic cells.

 

[prsk]

What's the difference with using FFs? I don't see any. The delay has to be generated in an "analog"way either, e.g. by logic cells.

Sure! But ok let me reframe the previous reply...if we were to use flip flops how would a delay be generated foe one fourth the clock time period?

 

[FvM]

It would be generated in the same way as with the simple XOR circuit. You can either delay the clock to the FF or it's output.

 

[albbg]

You can use two FF configured as Toggle type (f.i. a D-type with inverting output connected to D input).
One of the FF will have the Ck input directly connected to the input signal, the other one will be instead connected through an inverter gate (in this way one of the FF will work on the rising edge of the incoming signal and the other one on the falling edge). The just take the xor of the output of each FF.

It should work while the period of your signal is large enough to have the propagation delay of the gates to be negiglible.