[SOLVED] Does the vertical pnp is inferior with Substrate noise?

[mpig09]

Hi all:

I am design a bandgap circuit, and the process cmos logic process,
and the bjt is vertical pnp, does this type bjt is inferior with substrate
noise to effect bandgap voltage accuracy?

If the device is inferior with substrate noise to effect the bandgap voltage,
is there any layout solution to avoid substrate noise?

Thanks for your reply.
mpig

 

[erikl]

Re: Is the vertical pnp inferior to Substrate noise?

I am design a bandgap circuit, and the process cmos logic process,
and the bjt is vertical pnp, does this type bjt is inferior with substrate
noise to effect bandgap voltage accuracy?

Yes, it is - because of the low-ohmic substrate resistivity used for CMOS logic processes.
But I guess you have no choice - there's probably no other pnp BJT available.

is there any layout solution to avoid substrate noise?

You can't avoid substrate noise totally, but you can at least try and screen it: use at least one, better two guardrings around the pnp BJT array.

 

[dick_freebird]

Inferior to what? It's not like you have another viable
choice.

Collector being the substrate is not really any worse
than an isolated PNP tied to ground by metal, other
than that you don't get to choose -which- ground.
Other than by placement, and what else you allow to
inject substrate currents. And that its characteristics
as a transistor tend to be very poor, on purpose, and
likely poorly modeled.

I'm suspecting that on your first and second passes you
will find worse things than substrate noise when you
test it. Bet on the substrate BJT model being worse for
temperature fidelity than its lousy-enough room temp
accuracy and process control.

If I were you I'd be getting ahold of some real devices,
pick a unit geometry you like, and pull data and fit
models yourself. Unless the foundry asserts they've
done a reference-grade job of it, which for a digital
CMOS flow is unlikely investment on their part.

Otherwise you wait until fab-out to find out how
badly you've been misled by the provided model.

 

[mpig09]

Hi all:

Yes, I didn't have any other bjt choice for bandgap design.
Because there is a terminal of a vertical PNP is connect to substrate,
so I don't want substrate noise to interference the bandgap voltage directly.

Thanks for erikl 's layout suggestion, I will do it.
Thanks for dick_freebird's suggestion.

mpig

 

[rfsystem]

Hi all:

Yes, I didn't have any other bjt choice for bandgap design.
Because there is a terminal of a vertical PNP is connect to substrate,
so I don't want substrate noise to interference the bandgap voltage directly.

mpig

The process provide a vertical PNP where you could not conncet the collector to any potential because it is substrate. Depending on your design kit this vertical PNP is modelled as a diode or "Substrate PNP". The beta of this PNP would be between 0.5 and 2 so could not be used as current amplifier. For bandgaps where sum of a diode voltage and Vt resistor voltage drop is the target a different connection of the base of the PNP than the subtrate could be used to isolate substrate noise. So you connect the bases of bandgap core (PNPs) to your clean ground reference. Be aware that the base current is less than the emitter. The clean reference ground potential could in principle be higher than the substrate. So you can build a "floating" reference. But I think the noise isolation is your most wanted intention.

 

[mpig09]

Hi rfsystem :

Could you suggest:
1. the base and collector are connect to difference ground?
base connects to clean ground
collector has connect to substrate (dirty ground)
2. What mean build a "floating" reference?

Thanks for your reply.
mpig