Does the set up time of a flip flop changes in ASIC design ?

[vlsitechnology]

Hold and Setup

Does the set up time of a flip flop changes ?? when we are doing any project in asic design
I mean in any session ( prects, postcts, postroute and so on )does it changes
Reply me
Bye

 

[Amruth]

Re: Hold and Setup

hi,
yes it can change because it varies wit slew and load

i hope itll help u

 

[vlsitechnology]

Hold and Setup

But that never happens i guess bcz thsose values are already defined in the .lib right? so how does it change?

 

[lakshman.ar]

Hold and Setup

hi every1
Tsu of a FF doesnt vary whether u do it pre-layout or post- layout or .... b4 or after CTS !!

But the only timing between FF vary, cos there are
1) delay of cells
2) delay of interconnects

hwever only the delay caused due to the interconnects vary b4 and after payout !

cos in pre-layout wire lengths are estimated using WLM and in post -layout RC parasitics values are used ... hence timing analysis varies !

 

[sesl33]

Re: Hold and Setup

But that never happens i guess bcz thsose values are already defined in the .lib right? so how does it change?

After you have completed post-route, you can do back-annotation.
This will put in the wire load delay etc and hence, you can check your setup/hold time.