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Does the coprocessor 1 (FPU) of MIPS have its own datapath?

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matrixofdynamism

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The MIPS32 coprocessor 1 is used for floating point calculations. In the past this was a physically distinct processor but this is not the case anymore. The modern MIPS has the coprocessor 1 on the same die. I want to know what parts of the CPU are shared by the coprocessor 1?

MIPS pipeline would execute instructions in 5 stages, each taking 1 clock cycle. However, I do not think that a floating point calculation would be completed in 1 clock cycle (Execute stage). This would mean that the coprocessor 1 has a seperate decoder, register file, and ALU. Is this so? How do the CPU and Coprocessor 1 work in sync then?
 

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