I don't get it.
You are seriously violating the Absolute Maximum rating of Gnd - Gnd voltage tolerance of your driver ICs, and yet are not focusing on how to resolve an obvious problem.
Why is this ? How are you so sure that this exceeding of max rated voltage is not causing any problems ?
I don't get it too....that is - what you are saying "Gnd voltage tolerance of your driver ICs"? What do you mean by that? And why aren't you on holiday like everybody else? You don't have an auto-camper?
Since your circuit exceeds these voltage limits, especially during discharge in stage 3 and beyond, I have repeatedly pointed out to you to check this issue.
I live in India. We have different 'holidays'. We don't auto-camp. The land itself is our camp.
I have a new theory as to what is wrong, is there an EE in the house that could confirm it?
My new theory is that it's paracitics, so I added some stray inductance and capcitance to the simulation and it shows what I'm somewhat measuring. in this case I have 5 (c1-5) caps all charged up to 600V each, so I would expect 3KV output once all the Td's are ON, but here allmost 50% is lost due to paracitics.
View attachment 154419
Interesting.
I think it's time you posted some pics of your setup. Maybe there are some other obvious issues you have not considered as yet which might come to light with pics.
Parasitic capacitances surely matter, surprising that you start now to think about it.
2 x 2nF however isn't but a shot in the dark and should be justified with datasheet specs and measurements.
Are we still dealing with IGW15T120 IGBT switches? They have < 100 pF output capacitance, PCB capacitances per stage should be considerably lower.
No idea about gate driver and DC/DC parasitic capacitances. You have the circuit at your fingertips and can easily verify capacitance assumptions.
What 20khz are you referring to? And what is that yellow line on your pcb between drivers pads?
Sure, if parasitic capacitance causes the voltage drop, it must have a similar value. But is the capacitance value realistic?Not completely in the dark, I started with low values, and then I increased them until the simulation would show something I would recognize from the measurements.
Interesting.
My rudimentary analysis indicates that each of your caps would have to charge through your load, in sequence starting with your last stage and working backwards to the 1st stage. That would take many mS to complete.
Of course I'm just a noob, so could be totally wrong.
What do you mean by "would have"?
noob at giving expert advise? or noob at EE? I hope you are not giving expert advise without proper edabord certification and authorization ;-)
When you switch all the capacitors to join in series, their voltage differentials add up to extreme levels that can destroy components.
Node voltages change instantly as transistors are turned Off or On. Besides that, polarities can be positive or negative, depending on where you provide at low-ohm path.
It is easier to manage the first half of the cycle, that is, to connect each capacitor between supply and ground.
Then the second half of the cycle connects all capacitors in series. Notice that when you provide the most positive (final) capacitor a low-ohm path to ground (via reservoir capacitor or load), you instantly create extreme negative polarity at the first capacitor. (It happens even in a system running from a positive supply.)
This makes it difficult to create an effective switching scheme.
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