Does RESET signal need a buffer tree?

[spauls]

Read ASIC Synthesis by Himanshu Bhatnagar,
as reset is also going to all flops as one of the input, it is treated as high fanout network as clock

 

[FLEXcertifydll]

set the ideal_network for generating max fanout driven.

 

[shelkerahul]

Hi floatgrass

"backend tools can automatically deal with reset , eg socencounter."


You mean to say, we need not to build buffer tree separately, tool will take care in fanout optimization?
If it is so, then will reset be balance (problem of skew)


Rahul

 

[rameshsuthapalli]

hi all,

we have to build the tree on the reset networks.other wise the load on the reset pin is increased which will cause more delay on the reset net.while synthesis u can directly tell the tools as ideal_net.but in the backend u have to build the tree on the reset.


regards,
rameshs

 

[laglead]

It depends on synchrounous and asynchronous.

 

[intelvsamd]

Typically, RESET is asserted asyncronously, and de-asserted syncronously.
When Asserted, no timing violation occurs.
But, when de-asserted, if the load of RESET is too heavy or too light, it may violate recovery-timing or hold-timing. So, just like CTS, buffers need to be inserted .

 

[cihchenlin]

learn more

 

[cihchenlin]

all dff must turn off work at once

 

[snr_vlsi]

hi,

This is automatically taken care with high fan net synthesis which is done with a p&r tool like SOC encounter.

thx

snr_vlsi

 

[kimhj103]

I think if reset signal has large high fan-out as many as clock signal, we should make a tree structure for reset signal.

astHFCTS

 

[farhill]

i agree to the opinion that the thing which matters is the de-assertion of reset. a skew occurring at this time could result in malfunction. But anyone has ever indeed experienced such issue? looks most ppl here are just giving their opinion from thinking rather than real experience...

 

[pratap_v]

If the reset signal has a large load, i.e.., if the fanout is more, than there could be a timing vioaltion and also design rule violation like maximum constraint. To fix this one can do high fanout synthesis (HFN's) the same way as clock tree synthesis is done.
In the clock tree specification file you can specify nogating option which stop tracing reset signla through the next following stage gates.

---------- Post added at 09:47 ---------- Previous post was at 09:46 ----------

If the reset signal has a large load, i.e.., if the fanout is more, than there could be a timing vioaltion and also design rule violation like maximum constraint. To fix this one can do high fanout synthesis (HFN's) the same way as clock tree synthesis is done.
In the clock tree specification file you can specify nogating option which stop tracing reset signla through the next following stage gates.

 

[rca]

for reset generation, first of all, in our company the reset for rising edge FF if generate from a FF on the falling edge of the clock, to provide a half clock cycle of margin, and the P&R tool only process this net has High Fanout net. The incoming reset is connected to reset of the falling edge FF, and the D input is stuck to '1', so when the first clock falling edge arrive the reset is properly deasserted.
An other FF is used for the falling edge FF of the design.

 

[farhill]

This question should be considered application-wisely.
1. first application scenario is ASIC design.
a. assertion of reset. The skew between different paths could cause unexpected transient output at the moment of reset is asserted. If this is under control or harmless, no buffer tree required for reset assertion.
b. disassertion of reset. similar to assertion. As long as the unwanted output will be cleared by initialization, no need for fanout buffer either.
2. then let us look at circuit board application.
A major difference between circuit board reset design and ASIC is usually in circuit board the CPU takes much longer time to initialize itself before entering into operational state than peripherals such as flash, FPGA etc. So even the skew of reset between CPU and peripherals are big, it should be covered by the long init time of CPU after reset. Take flash as an example, whether or not a buffer is required is determined by if the time from the disassertion of reset to CPU starts to read flash is longer than the lag of flash reset compared with CPU reset, plus the flash self init time. Taking PIC as an example, it delays a T_startup which is 10us if using internal regulator after coming out of reset and before fetching data from flash.
In sum, in majority cases there is no need for a reset buffer tree. The view of the tree is needed should be just another plausible conclusion.