This question should be considered application-wisely.
1. first application scenario is ASIC design.
a. assertion of reset. The skew between different paths could cause unexpected transient output at the moment of reset is asserted. If this is under control or harmless, no buffer tree required for reset assertion.
b. disassertion of reset. similar to assertion. As long as the unwanted output will be cleared by initialization, no need for fanout buffer either.
2. then let us look at circuit board application.
A major difference between circuit board reset design and ASIC is usually in circuit board the CPU takes much longer time to initialize itself before entering into operational state than peripherals such as flash, FPGA etc. So even the skew of reset between CPU and peripherals are big, it should be covered by the long init time of CPU after reset. Take flash as an example, whether or not a buffer is required is determined by if the time from the disassertion of reset to CPU starts to read flash is longer than the lag of flash reset compared with CPU reset, plus the flash self init time. Taking PIC as an example, it delays a T_startup which is 10us if using internal regulator after coming out of reset and before fetching data from flash.
In sum, in majority cases there is no need for a reset buffer tree. The view of the tree is needed should be just another plausible conclusion.