Hi, I have the netlist of verilog which synthezied by synopsys dc. I found that there are some assign statement in the netlist(ex: assign a=b). As far as I know, the P&R tool cannot accept the netlist with assign statements insided. Do I miss something? How should I do in DC to eliminate assign statements when I write out the verilog netlist from DC? Thank s a lot for your kindly help.... :roll: :?
I have asked the company of design service, and their answer is none for accepting netlist with assign statement included. Thank a lot for linuxluo and all, I will try options of DC to see if works....
I have tried the options provided by linuxluo. Some assign statements disappeared by adding buffers. But there are assign statements which assign some signals to logic one or logic zero still exist. Can someone tell me how to erase the remaining assign statements in the netlist? thanks a lot for your kindly help...
Hi .. I had a pblm where in i had assign statements even if i tried the above options. I tried the below Approach and able to remove assign statements. So just give a try.
Maybe DC is not removing the assign statements because you have set dont touch on some modules or the clock/reset networks. in that case you will have to replace the assign statements manually/using scripts