Does P&R tools accept this verilog netlist?

[Memphis]

flatten verilog netlist

Hi, I have the netlist of verilog which synthezied by synopsys dc. I found that there are some assign statement in the netlist(ex: assign a=b). As far as I know, the P&R tool cannot accept the netlist with assign statements insided. Do I miss something? How should I do in DC to eliminate assign statements when I write out the verilog netlist from DC? Thank s a lot for your kindly help.... :roll: :?

 

[joe2moon]

Yes !

It seemed that the P&R tool did not support "assign" syntax before.

But, today's P&R tool seems to be able to handle this !

 

[cschen]

assign statements are not an issue for flat designs
but could cause back annotation issues for hierarchical verilog out.

 

[linuxluo]

hi,
u can set verilogout_no_tri true before synthesis.
set_fix_multiple_port_nets -feedthroughs

 

[Memphis]

I have asked the company of design service, and their answer is none for accepting netlist with assign statement included. Thank a lot for linuxluo and all, I will try options of DC to see if works....

 

[Nobody]

Here is the script i often use , dont forget to set the multple fix through the whole hierachically .

#
# Translation of script: fix_assign.scr
#

set design_list [find design *]
foreach_in_collection design $design_list {
current_design $design
set_fix_multiple_port_nets -all -buffer_constants
}

 

[Memphis]

I have tried the options provided by linuxluo. Some assign statements disappeared by adding buffers. But there are assign statements which assign some signals to logic one or logic zero still exist. Can someone tell me how to erase the remaining assign statements in the netlist? thanks a lot for your kindly help...

 

[zyphor]

you can set all module donot touch and then compile, all the assign will be deleted.

 

[keertiprasad1]

Hi .. I had a pblm where in i had assign statements even if i tried the above options. I tried the below Approach and able to remove assign statements. So just give a try.

read_verilog fix_mult.v
compile
write -f ddc -hier -out fix_mult.ddc
remove_design *
read_ddc fix_mult.ddc
link
set_fix_multiple_port_nets -all -buffer_constants [get_designs *]
compile
change_names -rules verilog -verbose -hier
write_file -f verilog -hierarchy -output fix_mult.vn

 

[chipmonkey]

Maybe DC is not removing the assign statements because you have set dont touch on some modules or the clock/reset networks. in that case you will have to replace the assign statements manually/using scripts