Hi,
For Mixed Signal Simulations tools are available from Cadence and Synopsys.
For Cadence IUS8.1 onwards you required separate AMS license, it requires total of 8 tokens. With this setup you can simulate the Analog and Digital designs (For analog either SPICE Netlist or Analog Models implemented in Verilog/VHDL-A plus Digital Verilog/VHDL-D is required). I dont know whether SystemVerilog has a Analog version.
Synopsys also has AMS tool in Scirocco, details I dont know check with any of the Synopsys AE.
(I'm totally ignorant the challenges in interfacing digital and analog interfaces)
-Paul