Note that the chip was DRC/LVS clean.
This, not the layout extracted simulation, is where I'd
be pointing the finger and swinging the bat. Because
as you say there was a miswiring and yet your layout
verification failed to catch it.
Either the instance(s) involving the psub guardring
had the same bad connection in the schematic, or the
schematic and layout did not in fact match. There ought
to have been a vdd-vss short chip-wide in the LVS results.
If the schematic carries the psub connection error (as
wire net property or as instance B terminal property,
as the case may be for the PDK in question) then a
schematic based simulation should show the diode lit
up. Presuming that the parasitic diodes are properly
modeled in the FET model subcircuit or compact model,
which is not to be assumed especially on non-I/O or
"digital" devices. This same model chain presumably
would be applied to an extracted view based simulation.
So one test would be to simulate a single NMOS device
in the application, with body attached to vdd potential.
You see either a ton of excess source current (!= drain)
or not. That tells you about general validity of D-B, S-B
diode model features implementation.
But I'd push into why you believe that LVS was clean
when you know there was a wiring fault in fact.