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Does a 3-phase phase-locked loop diagram possible for an AC to DC battery charger?

Hasan2017

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Hi there,

In order to achieve unity power factor control, the phase of the AC voltage needs to be obtained. The phase is obtained through a phase-locked loop (PLL).

Take a look for single phase control structure of the PLL ,

ppl_2.JPG


For such similar way I want to mention some of 3-phase equations, could you kindly elaborate it more ?


VSa = 1/3*(VSab-VSca);
VSb = 1/3*(VSbc-VSab);
VSc = 1/3*(VSca-VSbc);

VSalpha = 2/3*(VSa - (0.5*VSb) - (0.5*VSc));
VSbeta = 2/3 *(SQRT3_2*VSb - SQRT3_2*VSc);

VSq = VSalpha*COS_theta + VSbeta*SIN_theta;
VSd = -VSalpha*SIN_theta + VSbeta*COS_theta;

VSd_error = (VSd - VSd_ref);

freq_delta += (Kp_PLL*(VSd_error-AC_FREQ_PERR) + Ki_PLL*VSd_error);

Kp_PLL=0.1

p_VSd_error = VSd_error;

if(freq_delta > 5.) freq_delta = 5.;
if(freq_delta < -5.) freq_delta = -5.;

freq = ((AC_FREQ_NORMAL ? 50 : 60) + freq_delta);

freq_filtered = 0.99*freq_filtered + 0.01*freq;

theta += (PI2*freq_filtered*AC_TSW);
AC_TSW= 0.000033

Lets angle theta goes pi to 2*pi.

My one is very smart, kind of full bridge type but in in put and output it has inductor, first one might work as a filter, but output one is kind a of multilevel or mutually coupled. My be for suppressing ripple current .Lets say my input is 3p 380VAC, 60Hz, Main Transformer MTR runs at 20kHz, DC output should be 50-147 v, charging current 100A. Switching frequency is 120kHz, dead time120. Should have CC and CV mode of operation.
 

Easy peasy

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a phase lock loop is often used to generate a reference for the PFC stage - on very large rectifiers, >50kVA, the 6 switch bridge is some times used for harmonic cancellation of nearby non-linear loads as well as supplying the 700V bus for the down converter.
 

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I don't know about all of that but seems to me the PLL
just needs a /3 final stage from which you can get the
three reference edges by logic. Or, you put that /3 logic
outside the PLL and let the PLL lock (say) VSa_div with the
other two (VSb_div, VSc_div) "riding the train".

Checking those other two reference edges against
their real line phases' angles (zero crossings?) might
offer you some line-in phase fault detection.

How you do what you want to do with the rest of it,
I imagine discussion will ensue.
 

Hasan2017

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a phase lock loop is often used to generate a reference for the PFC stage - on very large rectifiers, >50kVA, the 6 switch bridge is some times used for harmonic cancellation of nearby non-linear loads as well as supplying the 700V bus for the down converter.

Yes well said. It has the 6 switch bridge , I think my system has leading PFC, because it does not have resistive load ( just when I test it with R), lets think battery works like a capacitor. Look at the datasheet of HF IGBT from infenon. I am using 6 pulses but with a different fashion. https://www.infineon.com/dgdl/Infin...N.pdf?fileId=db3a304327b8975001280604608b6165 For HF switching loss, spike or for other issue this IGBT module has small control circuit that has connection with DSP board.

See the real scenario
3_phase_ac_dc_bat_charger.png


I could provide you all high cap values and R as well. I feel some difference with this topology.
 

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Sorry - are you trying to repair something ? there is a separate space for repairs on this forum I think ...
--- Updated ---

Also the pic you posted has no need whatever for a PLL.
 

Hasan2017

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I don't know about all of that but seems to me the PLL
just needs a /3 final stage from which you can get the
three reference edges by logic. Or, you put that /3 logic
outside the PLL and let the PLL lock (say) VSa_div with the
other two (VSb_div, VSc_div) "riding the train".

Checking those other two reference edges against
their real line phases' angles (zero crossings?) might
offer you some line-in phase fault detection.

How you do what you want to do with the rest of it,
I imagine discussion will ensue.
If you take a look on the equation dont you imagine, A,B.C phase with 3 dimension converted to d,q vector field.
Take a look this for single phase ,
2_phase_ppl.JPG


Can you understand which part has reactive element and angular function. d, q both depends on theta.
Yes, my control system also has zero-cross detection but from firmware code it has been ignored. Some library gives you sampling angle table, and you can use it.

The reason why I have arise this question because, most of the research papers deals with L and R comes from AC source, my one has just 1 input inductor. The phase-shifter was used to adjust the phase angle over
the range 0-360°.

Now look at another scenario, where voltage and current is sensing from input.
사본 -Overall-circuit-configuration-of-the-universal-charger-with-the-signals-of-the-control.png


Read the publication also.
--- Updated ---

Also the pic you posted has no need whatever for a PLL

It should be mathematically reasonable. At least I have to make sure why PPL is not necessary in my code.
Control Law Accelerator cla of TI library task has option to configure your angle input . Angle has sampled in coding.
 

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  • A_Three-Phase_Controlled-Current_PWM_Converter_with_Leading_Power_Factor-1_210726_180141 (1).pdf
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FvM

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The controller for a three phase PFC or active frontend (AFE) should consider possible unbalanced mains voltages, deviations from symmetrical 3x120° input. A possible scheme locks the PLL to an average phase of mains lines, e.g. by averaging the phase error of alpha and beta component.

The controller should be able to generate assymetrical voltage feedforward and also react on voltage dips and drops.
 

Hasan2017

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The controller for a three phase PFC or active frontend (AFE) should consider possible unbalanced mains voltages, deviations from symmetrical 3x120° input. A possible scheme locks the PLL to an average phase of mains lines, e.g. by averaging the phase error of alpha and beta component.

The controller should be able to generate assymetrical voltage feedforward and also react on voltage dips and drops.
Yes. Very reasonable feedback. Thats what I wanted to figure out. PPL has significant contribution on phase error. DSP sampling techniques can identify it properly. I found only things for single phase, the equations I posted somehow it comes from any good journal.

Beside hermonic cancelation dont you think for such application zerocrossing is mandatory?
It looks like someone trying to make a zerocrossing graph in this firmware. May be PC HMI doesn't need it.
 

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