Doble-Gate MOSFETs simulation

[aapirzado]

Hi all,
For a Double Gate MOSFET, the width b/w 2 gates is known as Wsi. If I increase Wsi from 20 nanometers(nm) to 40, the gate loses control over channel and I can not deplete the device.It is logical to think, as the distance b/w 2 gates (Wsi) increases, it is harder for the gate to maintain control in the center of the channel (farthest from either gate). the gate loses the control over center of the channel.
can anyone help me explain this relationship in an analytical or physical way?
http://obrazki.elektroda.pl/4_1305728746.gif

 

[dick_freebird]

I stack FETs all the time in SOI and there's no problem. My
guess is that this has to do with specific lithography in the
"merged" device. I find it suspicious that you could have a
repeatable 20nm poly spacing (width, OK; space ???). In a
case like this a small amount of data beats any amount of
theory.

 

[aapirzado]

Dear Sir,
Thanks for ur rep. but i m using just Atlas sivalco to simulate the bahavoiur of DG MOSFET wiithout junctions.I hv 1um channel lenght n I vary the widht; Wsi from 10 to 40 nm. As i go further from 10 nm towards 40 nm, I find it dificlt to deplete the device bcz the distance b/w 2 gates increases. i believe, thr shd by some physics or maths that i m looking for. gate thicknes is 45nm and oxide is 15nm wide for all widht from 10 to 40 nm.