Do I have to compile the VHDL sub-module in Modelsim?

[tony_taoyh]

Anyone use ModelSim?

HI, Is there anyone using modelsim for VHDL?

When do compile, is it necessary to compile the sub-module first?

Can I compile top level first, then sub-module?

Now I begin to touch this tool..
Before, I use NCVHDL..


Thanks a lot.

Best Regards,
Tony

 

[arunragavan]

Re: Anyone use ModelSim?

What version of Modemsim are u using.. The latest is released the Modelsim version 6, after compiling the main module u can compile the testbench, as testbench has the vaues which u need to force during the compilation. You can even compile the testbench directly as its wud have the component name which is the entity name of the mainprogram this wud be way by which u shud compile the programs which u write programs and compile n modelsim. The best way wud be to install xilinx ISE 6.2 and then install modelsim the latest version and link its internal components. the frontend wud be given by xilinxs and wud surely u wud find it easy to work.

hope it helps

with regards,

 

[mediatek]

Anyone use ModelSim?

In my experience ,
you can put top and sub module+ testbench together in the same project ,
then choose compile all, it will show the module name + testbench name in work(default) , double click the testbench, you can trace the waveform
5.x already can do this
why you want to compile top first ??????

 

[abhineet22]

Anyone use ModelSim?

u must go in menu of model sim verson5.x and go on help in help all the yr doughts will be clear hope so.

 

[ikru26]

Re: Anyone use ModelSim?

REFER HELP IN MODELSIM .FIRST GO THROUGH THE TUTORIAL INBUILT IN MODLESIM AND THEN START CODING.IT IS VERY USEFUL


IF U DIDNT UNDERSTAND THEN I WILL TELL U PM

 

[shashi_reddy21]

Re: Anyone use ModelSim?

u set ur main module as top module and comile it ,it is not need to compile submodule s,it automatically compiles the submodule.

 

[rprince006]

Re: Anyone use ModelSim?

As you know, VHDL is different with Verilog at an important point that the order of compilation matters. Basically, it should be the order of entiny, architecture, and configuration files. And sub-modules are must compiled first.

I remember ModelSim can re-order the VHDL design source files automatically before compilation. I am not quite sure about it, however.

ModelSim is a nice tool, easy to use, and more important, it supprts mixed design using Verlog and VHDL. but Cadance's NC-verilog/NCVHDL and Synopsis's VCS are faster, I believe.

Regards,
rprince006

 

[laobian]

Anyone use ModelSim?

If some errors occurs, you can compile again, then the error maybe doesnot exist.

 

[roger]

Re: Anyone use ModelSim?

HI, Is there anyone using modelsim for VHDL?

When do compile, is it necessary to compile the sub-module first?

Can I compile top level first, then sub-module?

Now I begin to touch this tool..
Before, I use NCVHDL..


Thanks a lot.

Best Regards,
Tony

Yes, you have to compile sub-module first.

 

[amir81]

Anyone use ModelSim?

you should compile them in right order. if it sends error, you can use "compile order" and then "auto-generate" to allow modelsim to compile it in right order.

 

[maxsnail]

Re: Anyone use ModelSim?

model sim can do above you mentioned, it can load design all in library format,that is compiled before.

 

[cowslip]

Anyone use ModelSim?

Hi everyone,
I want to use Modelsim for simulating an example
application in a processor and use the .dat file to
load the application in memory. After at File ->Import I choose memory data, the dialog box asks for a *.mem
file. Why can't I just use the .dat file I have created?
How can I use this .dat file to load data in memory? if anyone knows the steps i'd be gratefull!! Thanks!

 

[cowslip]

Anyone use ModelSim?

Hi all,
Modelsim *.dat format is not a standard format for loading data in memory.

 

[nandhika]

Anyone use ModelSim?

hi

always u have to simulate sub modules first then top module........else it will show some error.......

trough model sim we can read the data from .txt i dnt have any idea about .dat.......if any one did share the idea..........

 

[deepu_s_s]

Re: Anyone use ModelSim?

its good to compile submodule first. coz when all the modules are integrated they should b error free. its difficult to understand where it went wrong.

---deepu.