DNL/INL relate to the uniformity of the DAC's transfer characteristic. Ideal DAC has uniform and equal steps in the output value for every bit of change in the input code. Any deviation form this uniformity causes DNL and INL. On their part, INL is a cause for static non-linearity in the DAC output. INL/DNL are not so much corner related (although there might be some impact) as they are mismatch related. So, you don't really need to run every possible corner but you do need to run exhaustive Monte-Carlo simulations. This being said it is best to simulate and then post-process the data, say in MATLAB. This will give you many more possibilities and flexibility too, something that you can not get simply from cadence.
However, having in mind also your other post about transistor OP simulation, I have the feeling you are in for a lot of serious reading. DAC is not something that is for careless design, nor is it an easy design, especially if resolution is high.