DNL and INL of a dac

[CAMALEAO]

Hi all.
Can anyone explain in their own words what does DNL and INL is? Why it is important and what kind of information it gives to us?

Now I am trying to do this in cadence. How do you calculate the DNL and INL of a current DAC using cadence?
Has anyone here tried to do this? Not using post processing, because I would like to use cadence due to the fact the number of corners are huge.

 

[KlausST]

Hi,

Where should we start?

Pleese choose one of the many ressources about DNL and INL you can find in the internet.
Useful sources are: wikipedia, documents from semicindyctor manufacturers, universities.
There even are vudeos explaining DNL and INL.
Many of those informations also refer to DAC and/or cadence.
Even here in the forum there already are more than 50 discussions about " DNL INL cadence".

Please go through a couple of them. Refer to one that suits you best. Tell us what you undersrand so far and what is not that clear.

Klaus

 

[CAMALEAO]

Fair enough. However I ws not able to find how to simulate this in Cadence. Are you able to provide a link with this? Thanks in advance.

 

[sutapanaki]

DNL/INL relate to the uniformity of the DAC's transfer characteristic. Ideal DAC has uniform and equal steps in the output value for every bit of change in the input code. Any deviation form this uniformity causes DNL and INL. On their part, INL is a cause for static non-linearity in the DAC output. INL/DNL are not so much corner related (although there might be some impact) as they are mismatch related. So, you don't really need to run every possible corner but you do need to run exhaustive Monte-Carlo simulations. This being said it is best to simulate and then post-process the data, say in MATLAB. This will give you many more possibilities and flexibility too, something that you can not get simply from cadence.

However, having in mind also your other post about transistor OP simulation, I have the feeling you are in for a lot of serious reading. DAC is not something that is for careless design, nor is it an easy design, especially if resolution is high.

 

[Puppet123]

https://www.edaboard.com/showthread.php?386542-DNL-INL-Measurement-in-Cadence-for-DAC

 

[CAMALEAO]

Thanks for the links. But what I am trying todo is using the cadence function DNL and INL to calculate this from a DC simulations (using the DC step).

Does anyone know how to do this? There a delay thing that doesn't make sense for DC. Then a step.

 

[Puppet123]

why are you doing it this way and not the generally accepted ways