Dear Friends,
After lot of hunting here and there I could come up with a code which utilizes the divider block built in Altera which I am using. I guess the code should work in other FPGAs also.
It takes an input signal and divides it by another signal. The output is also a signal. The only thing to make this work was to have appropriate type conversions.
Here's the code:
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity divtest2 is
port(inp,indv: in std_logic_vector(15 downto 0);
outp: out std_logic_vector(15 downto 0));
end divtest2;
architecture arch2 of divtest2 is
signal divval,temp1,temp2: integer range -16384 to 16383;
begin
temp1<= to_integer(signed(inp));
temp2<= to_integer(signed(indv));
divval<=temp1/temp2;
outp<=std_logic_vector(to_signed(divval,16));
end arch2;
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This can be easily modified to have clocked input and output. Hope you find it useful. :-D:-D