division in vhdl..showing error

[srini.pes]

Operator <DIVIDE> must have constant operands or first operand must be power of 2

i need to divide one data with 10.....
it showing this error....
how can i overcome this error please guide me

 

[qieda]

Hi,

normally a division can not be synthesized. So you need to implement some hardware dividing algorithm.

But I f you want to implement a divide by a constant e.g. by 10 you can do a multiplication with 1/10

You just have to use the correct number of bits.

I think you can do it like this

e.g your input is 16bit (max is 2^16-1 = 65535)
if you multiply with (2^16)/10 = 6554.
a 16bit * 16bit multiplication gives 32bit result
After the multiplication you shift by 16 to the right.
Now your result is again 16 bit

regards

 

[srini.pes]

Respected qieda.............
Thanking you so much for responding to my thread........
Actually this is my problem
i have implemented non restoring division algorithm for 32 bit...obviously it will take 32 cycles to complete the operation
now the problem is, in an intermediate stage i have this division operation.....
according to the situation this has to repeated for more than 4 times....if i use this algorithm block here its taking (32*4) more than 128 (min.) cycles...
It will give large delay....
so, i need to divide my clock into 32 clocks(called as clk2)........... like within one clock(main) division has to be completed................
other option is operating with clk2.............if so, slack is increasing
please guide me some thing to have a good design.........
Thanking you

 

[qieda]

Hi,

if you want to divide you clock period by 32, you need to multiply your frequency by 32.
To do this you will need a PLL.
Maybe you can modify your system that you supply the high frequency and do a clock divider to get your main frequency. This can be done with pure digital design.

But your design needs to work with this high frequency which is 32 times than your main frequency.

I think if this is not doable you have to look for a different dividing algorithm.
you can search the forum
e.g.
https://www.edaboard.com/threads/116890/
https://www.edaboard.com/threads/200720/
https://www.edaboard.com/threads/194878/
https://www.edaboard.com/threads/184079/
https://www.edaboard.com/threads/53741/
...

 

[abhiekulkarni]

Dear Friends,

After lot of hunting here and there I could come up with a code which utilizes the divider block built in Altera which I am using. I guess the code should work in other FPGAs also.
It takes an input signal and divides it by another signal. The output is also a signal. The only thing to make this work was to have appropriate type conversions.
Here's the code:
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;

entity divtest2 is
port(inp,indv: in std_logic_vector(15 downto 0);
outp: out std_logic_vector(15 downto 0));
end divtest2;


architecture arch2 of divtest2 is


signal divval,temp1,temp2: integer range -16384 to 16383;


begin

temp1<= to_integer(signed(inp));
temp2<= to_integer(signed(indv));
divval<=temp1/temp2;
outp<=std_logic_vector(to_signed(divval,16));


end arch2;
--------------------------------------------------------------------------------
This can be easily modified to have clocked input and output. Hope you find it useful. :-D:-D