what is the most efficient algorithm (area wise) for 16 bit/16 bit division in VHDL?

[Yihan]

what is the most efficient algorithm (area wise) for 16 bit/16 bit signed division for FPGA (VHDL)? Can somebody give me a couple of examples so I can compile them? I am new at programming FPGA's. Thanks.

 

[Yihan]

some people think the serial divider is the most efficient, is it right and why??

 

[FvM]

some people think the serial divider is the most efficient, is it right and why??

That's surely true, because it's just a subtractor, a shifter and a state machine. But it's slow compared to a full parallel divider.

 

[Yihan]

Do you know have any documentation that would support that? any good links? I have no luck googling... Thanks a lot

 

[FvM]

Serial divider IP can be found on the internet, at opencores and other places, and is also provided with some vendord libraries, e.g. from Xilinx.

 

[qieda]

Hi,
maybe this links helps

https://www.edaboard.com/threads/27948/
**broken link removed**)
High speed fixed point division in FPGAs
**broken link removed**

regards

 

[Yihan]

Are there any gate counts vs speed Tables somewhere for different division algorithms??

Thanks.

 

[Yihan]

Can someone give me a little bit more information about the serial divider? such as architecture...

---------- Post added at 10:31 ---------- Previous post was at 09:55 ----------

or a schematic of the serial divider?