[SOLVED] divider programme error 0 defination found for"/"

[nishantspanwar]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity div is
Port ( ad : in STD_LOGIC_VECTOR (16 downto 0);
bd : in STD_LOGIC_VECTOR (7 downto 0);
q : out STD_LOGIC_VECTOR (16 downto 0);
r : out STD_LOGIC_VECTOR (7 downto 0));
end div;

architecture Behavioral of div is
begin
q <= ad / bd;
r <= ad rem bd;

end Behavioral;


ERRORS:

ERROR:HDLCompiler:9 - "C:/Users/ankit/Desktop/Final Major project code/simple_mul/div.vhd" Line 41: Found 0 definitions for operator "/".
ERROR:HDLCompiler:9 - "C:/Users/ankit/Desktop/Final Major project code/simple_mul/div.vhd" Line 42: Found 0 definitions for operator "rem".
ERROR:HDLCompiler:854 - "C:/Users/ankit/Desktop/Final Major project code/simple_mul/div.vhd" Line 39: Unit <behavioral> ignored due to previous errors.

 

[FvM]

The operators are define in numeric_std for unsigned data type, but not for std_logic_vector.

- change all port signals to unsigned
- remove std_logic_unsigned library reference

 

[nishantspanwar]

The operators are define in numeric_std for unsigned data type, but not for std_logic_vector.

- change all port signals to unsigned
- remove std_logic_unsigned library reference

Thanks for the reply...
I appreciate you corrected the error...

But for my task i required std_logic as input data type and found a new algorithm for that.... :grin:\

Again Thanks a lot....:lol:

 

[FvM]

In this case you'll want to learn about type conversion.

 

[nishantspanwar]

In this case you'll want to learn about type conversion.

Wow....!!
is it possible to type cast in VHDL... as we can do in C language... I surely wish to learn....
Would you please provide some link or help me to start beggining with this topic...
.
It would be great if you can provide some refrence book for that...
Thanking you...

 

[TrickyDicky]

you can only do type conversion for closely related types. std_logic_vector, signed and unsigned are all arrays of std_logic, so you can just do a type conversion:

us <= unsigned(slv);
si <= signed(us);
slv <= std_logic_vector(si); --etc

When they are not closely related, you need a conversion function. For numeric_std types signed and unsigned, there is the to_integer and to_unsigned/signed functions:

us <= to_unsigned(some_integer, nbits);
some_integer <= to_integer( us);

so to convert from integer to std_logic_vector, you need a conversion function to get it to an unsigned/signed and then type convert to the slv:

slv <= std_logic_vector( to_unsigned( some_integer, nbits) );