Divider(4bit) verilog code for Spartan3E-XC3S100E

[srinivasandelta]

My 4 bit divider code is not working:
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Code Verilog - [expand]
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`timescale 1ns / 1ps
 
module  divider4t4(clock, divisor, dividend,quotient,reminder);
 
input clock;
input [3:0] divisor;
input [3:0] dividend;
 
output [3:0]quotient;
output [3:0]reminder;
 
reg [3:0]quotient;
reg [3:0]reminder;
reg [3:0]temp;
 
always@(posedge clock)
begin
    reminder = dividend;
    if(reminder >= 0)
        begin 
            reminder=reminder-divisor;
            temp=reminder;
            quotient = quotient + 1;
        end
    else
        reminder = temp;
end
 
assign [3:0]reminder = [3:0]reminder;
assign [3:0]quotient = [3:0]quotient;
 
endmodule

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Thank you in advance,

With regards,
Srinivasan

 

[FvM]

You apparently intend to write a sequential divider. But there's no sequence state machine in your code.
reminder is erroneously rewritten every cycle and quotient is never initialized.

Reconsider what you want to do, review examples from literature or try on your own.

 

[srinivasandelta]

First of all sorry for not posting the code under code tag.

I checked the forum for division program and help, but couldn't find any working code. All are incomplete and not executable.

While in the investigation, I got reminded about something I read about no solution for subtract operation through digital circuits of VLSI. I am not sure exactly where I read this.

But there is some basic point which illustrates the difficulty of implementing SUBTRACT function and not as straight forward way like addition.

Please can any one point out to any working code for Division/subtraction function/module in verilog syntax?