mostafa_m
Newbie level 3
I want to make A chain of inverters which begin and end with dff to make a needed delay in my research. I used libero Soc 10.1 which used Synplify to make its synthesis. The optimization which Synplify made remove my chain and replace it by 1 inverter (When the number of inverters is odd) or no inverter (When the number of inverters is even). Can anyone help me to fix it please?
Thanks
Thanks