[SOLVED] Direct Digital Synthesizer

[ali ghafoor]

i want some help about SFDR of DDS. how does phase noise of reference CLOCK affect the SFDR of DDS? would SFDR be same or different in following two cases:
1- if i use a clock source of 100MHz and use internal PLL of DDS to make the system reference clock equal to 1GHz(multiplier of 10). clock source phase noise is -140dBc/Hz @ 100kHz offset(after multiplication it will become -140+20log(10)=-120dBc/Hz)
2- if i use a clock source of 1GHz and bypass internal PLL of DDS. clock source phase noise is -120dBc/Hz @ 100kHz offset

would bypassing internal PLL of DDS improve SFDR of DDS (even if the ultimate phase noise of reference clock is same)??

 

[barry]

The DDS doesn't know if its clock is coming from a PLL or not, so if the output of the PLL is identical to the output of some other clock source, why would it make a difference? 120dBc/Hz is 120dBc/Hz.

 

[biff44]

Well, if you had a choice of using an extremely low noise crystal or saw oscillator at 100 MHz, or a crappy integrated VCO with a pll trying to clean it up inside of the DDS, which one would u choose?

The phase noise will be AT LEAST 20 Log (Neffective) worse. But there are additional terms...quantization noise, small discrete spurs, digital jitter noise, aliasing noise/spurs, etc etc, so it will be worse than that in real life.

 

[ali ghafoor]

dear barry, i agree with you..but i found a paper contradicting this argument..i have attached the paper inhere..please refer to its section 5..and provide me with your answer

 

[barry]

I'm not sure where you are seeing a contradiction. It states that using the internal multiplier (PLL) will increase phase noise (as would be expected), and thus your performance would degrade. You were proposing using a source clock versus a PLL-derived clock where both had the SAME phase noise. Basically, you can get a reference oscillator with much better phase noise than the output of a PLL will give you.