Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Simulation methodology for fractional-N synthesizer

Status
Not open for further replies.
Joined
Jul 11, 2021
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
71
What is the best method to simulate fractional-N synthesizers?
I would like to observe the shifts in average output frequency when I change the divide cycles of the programmable divider. I have attempted plotting the DFT of the output but this does not seem to be working because the output has different frequencies at different points in time. Please suggest ways to simulate the same in cadence virtuoso.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top