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Simulation methodology for fractional-N synthesizer

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What is the best method to simulate fractional-N synthesizers?
I would like to observe the shifts in average output frequency when I change the divide cycles of the programmable divider. I have attempted plotting the DFT of the output but this does not seem to be working because the output has different frequencies at different points in time. Please suggest ways to simulate the same in cadence virtuoso.
 

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