Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
If you talk about "6-bits Digital Integrated Attenuators" , they are very low Power and manufacturer normally mentions this power handling capacity being as P1dB ( or IIP3) so the attenuator can handle a power level around this point.
well for the purposes of a maximum junction temperature calculation, since these are designed to have a fairly good return loss over the entire range of attenuation settings....you want to assume 100% of the incident power is absorbed onto the chip.
to further look for the worst case situation, assume that all of it is absorbed in the input bit.
so depending on how the device is designed, like Pi network, etc, assume that the power is split between three FETS inside on bit one. then assume some sort of horrifically bad thermal resistance, like say 100 deg C/watt (since they are designed to be low power devices). and there you are.
example: One watt in, bit one is a 15 dB on off bit. one watt divided by 3 is 1/3 watt.
so each of the three resistors in the bit one attenuator section get 0.33W * 100 Deg C/watt = 33 deg C junction tempterature rise to the package mounting surface.
you could get a more accurate prediction if you contacted the manufacturer and asked for specific thermal resistance values for that particular packaged device