It looks kooky to me, if the PMOS meddles at all then
your current mirroring will be bent. -Maybe- there's a
model corner or settings that will give some desired
(non-1:1) transfer function at the far end of the bias
or maybe they really do want voltages and think that
"min(VTN, |VTP|)" offers a minimum-production-
variability (which it might) of a cheesy reference
voltage that values layout area and/or not-needing-
resistors-let-alone-precision over absolute accuracy).
I expect if you cared about tolerance you'd go with
a bandgap but a +/-10% "TTL threshold reference"
might well be made this way. Though I'd go with a
series NMOS+PMOS stack first off, most likely.
Since we don't know your care-abouts, suggest you
mock up a few alternatives and see what works best
at the far end of it all where specs probably define
a desired outcome.