awais107
Newbie level 6
Hi
I need some guidance regarding the implementation of Digital Leaky Integrator (First order IIR digital LPF) using full custom flow. I implemented the following:
https://www.physi.uni-heidelberg.de/~angelov/VHDL/VHDL_SS09_Teil06.pdf (slide 32)
Attached (Doc4.docx )
But the simulation in cadence take too much time and don't finish at all. I want to make a IIR digital LPF having cut-off frequency of 0.01Hz.
Awais
I need some guidance regarding the implementation of Digital Leaky Integrator (First order IIR digital LPF) using full custom flow. I implemented the following:
https://www.physi.uni-heidelberg.de/~angelov/VHDL/VHDL_SS09_Teil06.pdf (slide 32)
Attached (Doc4.docx )
But the simulation in cadence take too much time and don't finish at all. I want to make a IIR digital LPF having cut-off frequency of 0.01Hz.
Awais