FecP
Newbie level 6
The input clock is at 50 Mhz and I need the output (clk) at 25 Mhz.
If the clocked output isn't "LOCKED" , should a new reset signal be sent every clock cycle? I've used the enable counter to provide a delay between successive reset pulses i.e(give clock manager time to lock)? And a shift register to make the rst_in to last 3 seconds.
P.S. Is this the right way to reset a DCM? Wouldn't it be better if I tied the DCM 'rst_in' to the external reset? assign rst_in = RESET (From FPGA button)?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 DigitalClockManager instance_name ( .CLKIN_IN(CLK_50MHZ), .RST_IN(rst_in), .CLKFX_OUT(clk), .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT), .CLK0_OUT(), .LOCKED_OUT(LOCKED) ); BUFG buffer (.I(CLKIN_IBUFG_OUT), .O(CLKIN)); always @ (posedge CLKIN) begin if(RESET) begin enable <= 0; SR[0] <= 0; end else begin enable <= enable + 1; if(!LOCKED && !enable) SR[0] <= 1; else SR[0] <= 0; end end always @ (posedge CLKIN) begin SR <= SR >> 1; end assign rst_in = (SR[2] | SR[1] | SR[0]); //assert reset for 3 clock cyles
If the clocked output isn't "LOCKED" , should a new reset signal be sent every clock cycle? I've used the enable counter to provide a delay between successive reset pulses i.e(give clock manager time to lock)? And a shift register to make the rst_in to last 3 seconds.
P.S. Is this the right way to reset a DCM? Wouldn't it be better if I tied the DCM 'rst_in' to the external reset? assign rst_in = RESET (From FPGA button)?